add more and significantly better comments to the rest of the machineinstr

flags that can be set.  Add predicates for the ones lacking it, and switch
some clients over to using the predicates instead of Flags directly.

llvm-svn: 45690

2 files changed, 2 insertions, 2 deletions

diff --git a/llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp b/llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp
index df6503fd144..06bf010ba0e 100644
--- a/llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp
@@ -710,7 +710,7 @@ void ScheduleDAG::EmitNode(SDNode *Node, unsigned InstanceNo,
     }
 
     // Now that we have emitted all operands, emit this instruction itself.
-    if ((II.Flags & M_USES_CUSTOM_DAG_SCHED_INSERTION) == 0) {
+    if (!II.usesCustomDAGSchedInsertionHook()) {
       BB->insert(BB->end(), MI);
     } else {
       // Insert this instruction into the end of the basic block, potentially
diff --git a/llvm/lib/CodeGen/TwoAddressInstructionPass.cpp b/llvm/lib/CodeGen/TwoAddressInstructionPass.cpp
index bc8d62e6d9b..e77b95eeb9f 100644
--- a/llvm/lib/CodeGen/TwoAddressInstructionPass.cpp
+++ b/llvm/lib/CodeGen/TwoAddressInstructionPass.cpp
@@ -172,7 +172,7 @@ bool TwoAddressInstructionPass::runOnMachineFunction(MachineFunction &MF) {
 
             // If this instruction is potentially convertible to a true
             // three-address instruction,
-            if (TID->Flags & M_CONVERTIBLE_TO_3_ADDR) {
+            if (TID->isConvertibleTo3Addr()) {
               // FIXME: This assumes there are no more operands which are tied
               // to another register.
 #ifndef NDEBUG