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authorPirama Arumuga Nainar <pirama@google.com>2016-10-20 17:56:36 +0000
committerPirama Arumuga Nainar <pirama@google.com>2016-10-20 17:56:36 +0000
commit05b0f93ad33dd5df9f69ae5eb0b48d9f76304eb2 (patch)
tree8d4875053a1fa5aa9359e7738d541a6bd6388f46 /llvm/lib/CodeGen
parentbadd5b31b733febc58644d3fdbb23d1b448aeadb (diff)
downloadbcm5719-llvm-05b0f93ad33dd5df9f69ae5eb0b48d9f76304eb2.tar.gz
bcm5719-llvm-05b0f93ad33dd5df9f69ae5eb0b48d9f76304eb2.zip
Fix *_EXTEND_VECTOR_INREG legalization
Summary: While promoting *_EXTEND_VECTOR_INREG nodes whose inputs are already promoted, perform the appropriate sign extension for the promoted node before doing the *_EXTEND_VECTOR_INREG operation. If not, the undefined high-order bits of the promoted operand may (a) be garbage inc ase of zext) or (b) contribute the wrong sign-bit (in case of sext) Updated the promote-vec3.ll test after this change. The diff shows explicit zeroing in case of zext and intermediate sign extension in case of sext. Reviewers: RKSimon Subscribers: llvm-commits, srhines Differential Revision: https://reviews.llvm.org/D25790 llvm-svn: 284752
Diffstat (limited to 'llvm/lib/CodeGen')
-rw-r--r--llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp22
1 files changed, 19 insertions, 3 deletions
diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
index 41ca0b462f6..0669536ec13 100644
--- a/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
@@ -3349,11 +3349,27 @@ SDValue DAGTypeLegalizer::PromoteIntRes_EXTEND_VECTOR_INREG(SDNode *N) {
SDLoc dl(N);
- // For operands whose TypeAction is to promote, the promoted node to construct
- // a new *_EXTEND_VECTOR_INREG node.
+ // For operands whose TypeAction is to promote, extend the promoted node
+ // appropriately (ZERO_EXTEND or SIGN_EXTEND) from the original pre-promotion
+ // type, and then construct a new *_EXTEND_VECTOR_INREG node to the promote-to
+ // type..
if (getTypeAction(N->getOperand(0).getValueType())
== TargetLowering::TypePromoteInteger) {
- SDValue Promoted = GetPromotedInteger(N->getOperand(0));
+ SDValue Promoted;
+
+ switch(N->getOpcode()) {
+ case ISD::SIGN_EXTEND_VECTOR_INREG:
+ Promoted = SExtPromotedInteger(N->getOperand(0));
+ break;
+ case ISD::ZERO_EXTEND_VECTOR_INREG:
+ Promoted = ZExtPromotedInteger(N->getOperand(0));
+ break;
+ case ISD::ANY_EXTEND_VECTOR_INREG:
+ Promoted = GetPromotedInteger(N->getOperand(0));
+ break;
+ default:
+ llvm_unreachable("Node has unexpected Opcode");
+ }
return DAG.getNode(N->getOpcode(), dl, NVT, Promoted);
}
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