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authorEvan Cheng <evan.cheng@apple.com>2008-06-16 07:33:11 +0000
committerEvan Cheng <evan.cheng@apple.com>2008-06-16 07:33:11 +0000
commit03553bb59af15fbbc49a162cab2314095f674bd5 (patch)
treec32f8764934cd95156f9a68a48839240e7d30540 /llvm/lib/CodeGen
parente546c55e5928dd9d19919634d4755dfd8e67f80b (diff)
downloadbcm5719-llvm-03553bb59af15fbbc49a162cab2314095f674bd5.tar.gz
bcm5719-llvm-03553bb59af15fbbc49a162cab2314095f674bd5.zip
Add option to commuteInstruction() which forces it to create a new (commuted) instruction.
llvm-svn: 52308
Diffstat (limited to 'llvm/lib/CodeGen')
-rw-r--r--llvm/lib/CodeGen/TargetInstrInfoImpl.cpp19
1 files changed, 17 insertions, 2 deletions
diff --git a/llvm/lib/CodeGen/TargetInstrInfoImpl.cpp b/llvm/lib/CodeGen/TargetInstrInfoImpl.cpp
index 1bb08ab93bb..ff9c129994e 100644
--- a/llvm/lib/CodeGen/TargetInstrInfoImpl.cpp
+++ b/llvm/lib/CodeGen/TargetInstrInfoImpl.cpp
@@ -14,24 +14,39 @@
#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/CodeGen/MachineInstr.h"
+#include "llvm/CodeGen/MachineInstrBuilder.h"
using namespace llvm;
// commuteInstruction - The default implementation of this method just exchanges
// operand 1 and 2.
-MachineInstr *TargetInstrInfoImpl::commuteInstruction(MachineInstr *MI) const {
+MachineInstr *TargetInstrInfoImpl::commuteInstruction(MachineInstr *MI,
+ bool NewMI) const {
assert(MI->getOperand(1).isRegister() && MI->getOperand(2).isRegister() &&
"This only knows how to commute register operands so far");
unsigned Reg1 = MI->getOperand(1).getReg();
unsigned Reg2 = MI->getOperand(2).getReg();
bool Reg1IsKill = MI->getOperand(1).isKill();
bool Reg2IsKill = MI->getOperand(2).isKill();
+ bool ChangeReg0 = false;
if (MI->getOperand(0).getReg() == Reg1) {
// Must be two address instruction!
assert(MI->getDesc().getOperandConstraint(0, TOI::TIED_TO) &&
"Expecting a two-address instruction!");
Reg2IsKill = false;
- MI->getOperand(0).setReg(Reg2);
+ ChangeReg0 = true;
+ }
+
+ if (NewMI) {
+ // Create a new instruction.
+ unsigned Reg0 = ChangeReg0 ? Reg2 : MI->getOperand(0).getReg();
+ bool Reg0IsDead = MI->getOperand(0).isDead();
+ return BuildMI(MI->getDesc()).addReg(Reg0, true, false, false, Reg0IsDead)
+ .addReg(Reg2, false, false, Reg2IsKill)
+ .addReg(Reg1, false, false, Reg1IsKill);
}
+
+ if (ChangeReg0)
+ MI->getOperand(0).setReg(Reg2);
MI->getOperand(2).setReg(Reg1);
MI->getOperand(1).setReg(Reg2);
MI->getOperand(2).setIsKill(Reg1IsKill);
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