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author | Sanjay Patel <spatel@rotateright.com> | 2016-10-14 14:26:47 +0000 |
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committer | Sanjay Patel <spatel@rotateright.com> | 2016-10-14 14:26:47 +0000 |
commit | 00fc7a61598ee5ce6afe0d5290faf1eb767eed52 (patch) | |
tree | 7ebe8f340e34eb9d491382acdc23424385d036b9 /llvm/lib/CodeGen | |
parent | 7b4e4afb617be9da9a0b46760ee1142a13551ec4 (diff) | |
download | bcm5719-llvm-00fc7a61598ee5ce6afe0d5290faf1eb767eed52.tar.gz bcm5719-llvm-00fc7a61598ee5ce6afe0d5290faf1eb767eed52.zip |
[DAG] add folds for negated shifted sign bit
The same folds exist in InstCombine already.
This came up as part of:
https://reviews.llvm.org/D25485
llvm-svn: 284239
Diffstat (limited to 'llvm/lib/CodeGen')
-rw-r--r-- | llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp | 13 |
1 files changed, 13 insertions, 0 deletions
diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp index 360ce8f1be0..031edb615b8 100644 --- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp @@ -1954,6 +1954,19 @@ SDValue DAGCombiner::visitSUB(SDNode *N) { DAG.getConstant(-N1C->getAPIntValue(), DL, VT)); } + // Right-shifting everything out but the sign bit followed by negation is the + // same as flipping arithmetic/logical shift type without the negation: + // -(X >>u 31) -> (X >>s 31) + // -(X >>s 31) -> (X >>u 31) + if (isNullConstantOrNullSplatConstant(N0) && + (N1->getOpcode() == ISD::SRA || N1->getOpcode() == ISD::SRL)) { + ConstantSDNode *ShiftAmt = isConstOrConstSplat(N1.getOperand(1)); + if (ShiftAmt && ShiftAmt->getZExtValue() == VT.getScalarSizeInBits() - 1) { + auto NewOpcode = N1->getOpcode() == ISD::SRA ? ISD::SRL :ISD::SRA; + return DAG.getNode(NewOpcode, DL, VT, N1.getOperand(0), N1.getOperand(1)); + } + } + // Canonicalize (sub -1, x) -> ~x, i.e. (xor x, -1) if (isAllOnesConstantOrAllOnesSplatConstant(N0)) return DAG.getNode(ISD::XOR, DL, VT, N1, N0); |