diff options
author | Lang Hames <lhames@gmail.com> | 2009-11-18 20:31:20 +0000 |
---|---|---|
committer | Lang Hames <lhames@gmail.com> | 2009-11-18 20:31:20 +0000 |
commit | e9e0cd4e27149ab4e785126a3eac5a6f2e2a1b27 (patch) | |
tree | 6781b1db00f2a6381c0b6e67b4fc72598382ce6a /llvm/lib/CodeGen/VirtRegRewriter.cpp | |
parent | 2d4371d666c38d29325079b0b63fade78a11cba9 (diff) | |
download | bcm5719-llvm-e9e0cd4e27149ab4e785126a3eac5a6f2e2a1b27.tar.gz bcm5719-llvm-e9e0cd4e27149ab4e785126a3eac5a6f2e2a1b27.zip |
Fixed the in-place spiller and trivial rewriter, which had been broken by the recent SlotIndexes work.
llvm-svn: 89238
Diffstat (limited to 'llvm/lib/CodeGen/VirtRegRewriter.cpp')
-rw-r--r-- | llvm/lib/CodeGen/VirtRegRewriter.cpp | 31 |
1 files changed, 21 insertions, 10 deletions
diff --git a/llvm/lib/CodeGen/VirtRegRewriter.cpp b/llvm/lib/CodeGen/VirtRegRewriter.cpp index ec0abd137d6..c836286f60f 100644 --- a/llvm/lib/CodeGen/VirtRegRewriter.cpp +++ b/llvm/lib/CodeGen/VirtRegRewriter.cpp @@ -77,27 +77,38 @@ struct TrivialRewriter : public VirtRegRewriter { DEBUG(MF.dump()); MachineRegisterInfo *mri = &MF.getRegInfo(); + const TargetRegisterInfo *tri = MF.getTarget().getRegisterInfo(); bool changed = false; for (LiveIntervals::iterator liItr = LIs->begin(), liEnd = LIs->end(); liItr != liEnd; ++liItr) { - if (TargetRegisterInfo::isVirtualRegister(liItr->first)) { - if (VRM.hasPhys(liItr->first)) { - unsigned preg = VRM.getPhys(liItr->first); - mri->replaceRegWith(liItr->first, preg); - mri->setPhysRegUsed(preg); - changed = true; - } + const LiveInterval *li = liItr->second; + unsigned reg = li->reg; + + if (TargetRegisterInfo::isPhysicalRegister(reg)) { + if (!li->empty()) + mri->setPhysRegUsed(reg); } else { - if (!liItr->second->empty()) { - mri->setPhysRegUsed(liItr->first); + if (!VRM.hasPhys(reg)) + continue; + unsigned pReg = VRM.getPhys(reg); + mri->setPhysRegUsed(pReg); + for (MachineRegisterInfo::reg_iterator regItr = mri->reg_begin(reg), + regEnd = mri->reg_end(); regItr != regEnd;) { + MachineOperand &mop = regItr.getOperand(); + assert(mop.isReg() && mop.getReg() == reg && "reg_iterator broken?"); + ++regItr; + unsigned subRegIdx = mop.getSubReg(); + unsigned pRegOp = subRegIdx ? tri->getSubReg(pReg, subRegIdx) : pReg; + mop.setReg(pRegOp); + mop.setSubReg(0); + changed = true; } } } - DEBUG(errs() << "**** Post Machine Instrs ****\n"); DEBUG(MF.dump()); |