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authorSanjay Patel <spatel@rotateright.com>2018-03-14 15:28:48 +0000
committerSanjay Patel <spatel@rotateright.com>2018-03-14 15:28:48 +0000
commit5773ac3ee8a05331207c542f0570a211b292d8c1 (patch)
tree2b803b53f1a2acb80ea5810956ebd1734332a608 /llvm/lib/CodeGen/TargetSubtargetInfo.cpp
parent36e34a99c72a3aa62ddf38b6161ae6c3a860eaf1 (diff)
downloadbcm5719-llvm-5773ac3ee8a05331207c542f0570a211b292d8c1.tar.gz
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[CodeGen] allow printing of zero latency in sched comments
I don't know how to expose this in a test. There are ARM / AArch64 sched classes that include zero latency instructions, but I'm not seeing sched info printed for those targets. X86 will almost certainly have these soon (see PR36671), but no model has 'let Latency = 0' currently. llvm-svn: 327518
Diffstat (limited to 'llvm/lib/CodeGen/TargetSubtargetInfo.cpp')
-rw-r--r--llvm/lib/CodeGen/TargetSubtargetInfo.cpp8
1 files changed, 3 insertions, 5 deletions
diff --git a/llvm/lib/CodeGen/TargetSubtargetInfo.cpp b/llvm/lib/CodeGen/TargetSubtargetInfo.cpp
index a72d7ebaed4..0d7940d767c 100644
--- a/llvm/lib/CodeGen/TargetSubtargetInfo.cpp
+++ b/llvm/lib/CodeGen/TargetSubtargetInfo.cpp
@@ -68,17 +68,15 @@ bool TargetSubtargetInfo::useAA() const {
}
static std::string createSchedInfoStr(unsigned Latency,
- Optional<double> RThroughput) {
+ Optional<double> RThroughput) {
static const char *SchedPrefix = " sched: [";
std::string Comment;
raw_string_ostream CS(Comment);
- if (Latency > 0 && RThroughput.hasValue())
+ if (RThroughput.hasValue())
CS << SchedPrefix << Latency << format(":%2.2f", RThroughput.getValue())
<< "]";
- else if (Latency > 0)
+ else
CS << SchedPrefix << Latency << ":?]";
- else if (RThroughput.hasValue())
- CS << SchedPrefix << "?:" << RThroughput.getValue() << "]";
CS.flush();
return Comment;
}
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