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author | Andrea Di Biagio <Andrea_DiBiagio@sn.scee.net> | 2018-04-15 17:32:17 +0000 |
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committer | Andrea Di Biagio <Andrea_DiBiagio@sn.scee.net> | 2018-04-15 17:32:17 +0000 |
commit | b9acf13907c877a61abc37f2a9ec621ab0dd9d5b (patch) | |
tree | 2359a746cddea87a08062e5735da2ebabae0a259 /llvm/lib/CodeGen/TargetSchedule.cpp | |
parent | 6c3af659a296d61ecba2fbf83d67e7292a601f69 (diff) | |
download | bcm5719-llvm-b9acf13907c877a61abc37f2a9ec621ab0dd9d5b.tar.gz bcm5719-llvm-b9acf13907c877a61abc37f2a9ec621ab0dd9d5b.zip |
[MC] Moved all the remaining logic that computed instruction latency and reciprocal throughput from TargetSchedModel to MCSchedModel.
TargetSchedModel now always delegates to MCSchedModel the computation of
instruction latency and reciprocal throughput.
No functional change intended.
llvm-svn: 330099
Diffstat (limited to 'llvm/lib/CodeGen/TargetSchedule.cpp')
-rw-r--r-- | llvm/lib/CodeGen/TargetSchedule.cpp | 45 |
1 files changed, 10 insertions, 35 deletions
diff --git a/llvm/lib/CodeGen/TargetSchedule.cpp b/llvm/lib/CodeGen/TargetSchedule.cpp index b8f284880af..5b6f72fbb35 100644 --- a/llvm/lib/CodeGen/TargetSchedule.cpp +++ b/llvm/lib/CodeGen/TargetSchedule.cpp @@ -260,16 +260,8 @@ TargetSchedModel::computeInstrLatency(const MCSchedClassDesc &SCDesc) const { unsigned TargetSchedModel::computeInstrLatency(unsigned Opcode) const { assert(hasInstrSchedModel() && "Only call this function with a SchedModel"); - unsigned SCIdx = TII->get(Opcode).getSchedClass(); - const MCSchedClassDesc *SCDesc = SchedModel.getSchedClassDesc(SCIdx); - - if (!SCDesc->isValid()) - return 0; - if (!SCDesc->isVariant()) - return computeInstrLatency(*SCDesc); - - llvm_unreachable("No MI sched latency"); + return SchedModel.computeInstrLatency(*STI, SCIdx); } unsigned @@ -324,42 +316,25 @@ computeOutputLatency(const MachineInstr *DefMI, unsigned DefOperIdx, return 0; } -static Optional<double> -getRThroughputFromItineraries(unsigned schedClass, - const InstrItineraryData *IID){ - Optional<double> Throughput; - - for (const InstrStage *IS = IID->beginStage(schedClass), - *E = IID->endStage(schedClass); - IS != E; ++IS) { - if (IS->getCycles()) { - double Temp = countPopulation(IS->getUnits()) * 1.0 / IS->getCycles(); - Throughput = Throughput.hasValue() - ? std::min(Throughput.getValue(), Temp) - : Temp; - } +Optional<double> +TargetSchedModel::computeReciprocalThroughput(const MachineInstr *MI) const { + if (hasInstrItineraries()) { + unsigned SchedClass = MI->getDesc().getSchedClass(); + return MCSchedModel::getReciprocalThroughput(SchedClass, + *getInstrItineraries()); } - if (Throughput.hasValue()) - // We need reciprocal throughput that's why we return such value. - return 1 / Throughput.getValue(); - return Throughput; -} -Optional<double> -TargetSchedModel::computeInstrRThroughput(const MachineInstr *MI) const { - if (hasInstrItineraries()) - return getRThroughputFromItineraries(MI->getDesc().getSchedClass(), - getInstrItineraries()); if (hasInstrSchedModel()) return MCSchedModel::getReciprocalThroughput(*STI, *resolveSchedClass(MI)); return Optional<double>(); } Optional<double> -TargetSchedModel::computeInstrRThroughput(unsigned Opcode) const { +TargetSchedModel::computeReciprocalThroughput(unsigned Opcode) const { unsigned SchedClass = TII->get(Opcode).getSchedClass(); if (hasInstrItineraries()) - return getRThroughputFromItineraries(SchedClass, getInstrItineraries()); + return MCSchedModel::getReciprocalThroughput(SchedClass, + *getInstrItineraries()); if (hasInstrSchedModel()) { const MCSchedClassDesc &SCDesc = *SchedModel.getSchedClassDesc(SchedClass); if (SCDesc.isValid() && !SCDesc.isVariant()) |