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| author | Sjoerd Meijer <sjoerd.meijer@arm.com> | 2018-03-19 13:35:25 +0000 |
|---|---|---|
| committer | Sjoerd Meijer <sjoerd.meijer@arm.com> | 2018-03-19 13:35:25 +0000 |
| commit | d16037d9bbe27639add9fb48b993b2048d2d1031 (patch) | |
| tree | 9429549cee2b79bea949844403ebfec19ac109ac /llvm/lib/CodeGen/TargetPassConfig.cpp | |
| parent | 116c30918142a5ee47299e714b3ae31e0ecaa0b9 (diff) | |
| download | bcm5719-llvm-d16037d9bbe27639add9fb48b993b2048d2d1031.tar.gz bcm5719-llvm-d16037d9bbe27639add9fb48b993b2048d2d1031.zip | |
[ARM] Support for v4f16 and v8f16 vectors
This is the groundwork for adding the Armv8.2-A FP16 vector intrinsics, which
uses v4f16 and v8f16 vector operands and return values. All the moving parts
are tested with two intrinsics, a 1-operand v8f16 and a 2-operand v4f16
intrinsic. In a follow-up patch the rest of the intrinsics and tests will be
added.
Differential Revision: https://reviews.llvm.org/D44538
llvm-svn: 327839
Diffstat (limited to 'llvm/lib/CodeGen/TargetPassConfig.cpp')
0 files changed, 0 insertions, 0 deletions
