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| author | QingShan Zhang <qshanz@cn.ibm.com> | 2020-01-03 03:26:41 +0000 |
|---|---|---|
| committer | QingShan Zhang <qshanz@cn.ibm.com> | 2020-01-03 03:26:41 +0000 |
| commit | 2133d3c5586b1a782e4d8e2a34c9f501499705cf (patch) | |
| tree | e1a37e6a0781cbe289b8ff7f4f75b7bcc75b16b2 /llvm/lib/CodeGen/TargetPassConfig.cpp | |
| parent | 60333a531799c0d0db1c3995bc784d2b314920ff (diff) | |
| download | bcm5719-llvm-2133d3c5586b1a782e4d8e2a34c9f501499705cf.tar.gz bcm5719-llvm-2133d3c5586b1a782e4d8e2a34c9f501499705cf.zip | |
[DAGCombine] Initialize the default operation action for SIGN_EXTEND_INREG for vector type as 'expand' instead of 'legal'
For now, we didn't set the default operation action for SIGN_EXTEND_INREG for
vector type, which is 0 by default, that is legal. However, most target didn't
have native instructions to support this opcode. It should be set as expand by
default, as what we did for ANY_EXTEND_VECTOR_INREG.
Differential Revision: https://reviews.llvm.org/D70000
Diffstat (limited to 'llvm/lib/CodeGen/TargetPassConfig.cpp')
0 files changed, 0 insertions, 0 deletions
