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authorAndrew Trick <atrick@apple.com>2012-09-17 23:00:42 +0000
committerAndrew Trick <atrick@apple.com>2012-09-17 23:00:42 +0000
commit8e7f202e32149f86bb15813398cc8f3b92b12387 (patch)
treef7a9c576229d0f8dfc51d9fbbbd548e2849078e6 /llvm/lib/CodeGen/TargetInstrInfoImpl.cpp
parent2b006e42319903437a3b2231b8c99eca5d940946 (diff)
downloadbcm5719-llvm-8e7f202e32149f86bb15813398cc8f3b92b12387.tar.gz
bcm5719-llvm-8e7f202e32149f86bb15813398cc8f3b92b12387.zip
Revert r164061-r164067. Most of the new subtarget emitter.
I have to work out the Target/CodeGen header dependencies before putting this back. llvm-svn: 164072
Diffstat (limited to 'llvm/lib/CodeGen/TargetInstrInfoImpl.cpp')
-rw-r--r--llvm/lib/CodeGen/TargetInstrInfoImpl.cpp14
1 files changed, 7 insertions, 7 deletions
diff --git a/llvm/lib/CodeGen/TargetInstrInfoImpl.cpp b/llvm/lib/CodeGen/TargetInstrInfoImpl.cpp
index 8ed66f70443..7e7f835040b 100644
--- a/llvm/lib/CodeGen/TargetInstrInfoImpl.cpp
+++ b/llvm/lib/CodeGen/TargetInstrInfoImpl.cpp
@@ -606,13 +606,13 @@ getOperandLatency(const InstrItineraryData *ItinData,
/// If we can determine the operand latency from the def only, without itinerary
/// lookup, do so. Otherwise return -1.
-int TargetInstrInfo::computeDefOperandLatency(
- const InstrItineraryData *ItinData,
- const MachineInstr *DefMI, bool FindMin) const {
+static int computeDefOperandLatency(
+ const TargetInstrInfo *TII, const InstrItineraryData *ItinData,
+ const MachineInstr *DefMI, bool FindMin) {
// Let the target hook getInstrLatency handle missing itineraries.
if (!ItinData)
- return getInstrLatency(ItinData, DefMI);
+ return TII->getInstrLatency(ItinData, DefMI);
// Return a latency based on the itinerary properties and defining instruction
// if possible. Some common subtargets don't require per-operand latency,
@@ -621,7 +621,7 @@ int TargetInstrInfo::computeDefOperandLatency(
// If MinLatency is valid, call getInstrLatency. This uses Stage latency if
// it exists before defaulting to MinLatency.
if (ItinData->SchedModel->MinLatency >= 0)
- return getInstrLatency(ItinData, DefMI);
+ return TII->getInstrLatency(ItinData, DefMI);
// If MinLatency is invalid, OperandLatency is interpreted as MinLatency.
// For empty itineraries, short-cirtuit the check and default to one cycle.
@@ -629,7 +629,7 @@ int TargetInstrInfo::computeDefOperandLatency(
return 1;
}
else if(ItinData->isEmpty())
- return defaultDefLatency(ItinData->SchedModel, DefMI);
+ return TII->defaultDefLatency(ItinData->SchedModel, DefMI);
// ...operand lookup required
return -1;
@@ -652,7 +652,7 @@ computeOperandLatency(const InstrItineraryData *ItinData,
const MachineInstr *UseMI, unsigned UseIdx,
bool FindMin) const {
- int DefLatency = computeDefOperandLatency(ItinData, DefMI, FindMin);
+ int DefLatency = computeDefOperandLatency(this, ItinData, DefMI, FindMin);
if (DefLatency >= 0)
return DefLatency;
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