diff options
author | Eric Christopher <echristo@gmail.com> | 2014-08-04 21:25:23 +0000 |
---|---|---|
committer | Eric Christopher <echristo@gmail.com> | 2014-08-04 21:25:23 +0000 |
commit | d913448b38bab6ace92ae5057b917eb57035f83b (patch) | |
tree | f2050928fa5994c44fab60d66e7d89e7cc7d7a4f /llvm/lib/CodeGen/TargetInstrInfo.cpp | |
parent | acc8ef273b1c3796b0fc7f19aa347115b4bc2ea4 (diff) | |
download | bcm5719-llvm-d913448b38bab6ace92ae5057b917eb57035f83b.tar.gz bcm5719-llvm-d913448b38bab6ace92ae5057b917eb57035f83b.zip |
Remove the TargetMachine forwards for TargetSubtargetInfo based
information and update all callers. No functional change.
llvm-svn: 214781
Diffstat (limited to 'llvm/lib/CodeGen/TargetInstrInfo.cpp')
-rw-r--r-- | llvm/lib/CodeGen/TargetInstrInfo.cpp | 17 |
1 files changed, 11 insertions, 6 deletions
diff --git a/llvm/lib/CodeGen/TargetInstrInfo.cpp b/llvm/lib/CodeGen/TargetInstrInfo.cpp index fc74899f479..2d8b656bb12 100644 --- a/llvm/lib/CodeGen/TargetInstrInfo.cpp +++ b/llvm/lib/CodeGen/TargetInstrInfo.cpp @@ -290,13 +290,15 @@ bool TargetInstrInfo::getStackSlotRange(const TargetRegisterClass *RC, Offset = 0; return true; } - unsigned BitSize = TM->getRegisterInfo()->getSubRegIdxSize(SubIdx); + unsigned BitSize = + TM->getSubtargetImpl()->getRegisterInfo()->getSubRegIdxSize(SubIdx); // Convert bit size to byte size to be consistent with // MCRegisterClass::getSize(). if (BitSize % 8) return false; - int BitOffset = TM->getRegisterInfo()->getSubRegIdxOffset(SubIdx); + int BitOffset = + TM->getSubtargetImpl()->getRegisterInfo()->getSubRegIdxOffset(SubIdx); if (BitOffset < 0 || BitOffset % 8) return false; @@ -305,7 +307,7 @@ bool TargetInstrInfo::getStackSlotRange(const TargetRegisterClass *RC, assert(RC->getSize() >= (Offset + Size) && "bad subregister range"); - if (!TM->getDataLayout()->isLittleEndian()) { + if (!TM->getSubtargetImpl()->getDataLayout()->isLittleEndian()) { Offset = RC->getSize() - (Offset + Size); } return true; @@ -498,7 +500,8 @@ TargetInstrInfo::foldMemoryOperand(MachineBasicBlock::iterator MI, const MachineOperand &MO = MI->getOperand(1-Ops[0]); MachineBasicBlock::iterator Pos = MI; - const TargetRegisterInfo *TRI = MF.getTarget().getRegisterInfo(); + const TargetRegisterInfo *TRI = + MF.getTarget().getSubtargetImpl()->getRegisterInfo(); if (Flags == MachineMemOperand::MOStore) storeRegToStackSlot(*MBB, Pos, MO.getReg(), MO.isKill(), FI, RC, TRI); @@ -653,8 +656,10 @@ bool TargetInstrInfo::isSchedulingBoundary(const MachineInstr *MI, // saves compile time, because it doesn't require every single // stack slot reference to depend on the instruction that does the // modification. - const TargetLowering &TLI = *MF.getTarget().getTargetLowering(); - const TargetRegisterInfo *TRI = MF.getTarget().getRegisterInfo(); + const TargetLowering &TLI = + *MF.getTarget().getSubtargetImpl()->getTargetLowering(); + const TargetRegisterInfo *TRI = + MF.getTarget().getSubtargetImpl()->getRegisterInfo(); if (MI->modifiesRegister(TLI.getStackPointerRegisterToSaveRestore(), TRI)) return true; |