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authorEvan Cheng <evan.cheng@apple.com>2011-06-27 21:26:13 +0000
committerEvan Cheng <evan.cheng@apple.com>2011-06-27 21:26:13 +0000
commit8d71a757774daf1558086b6133ce4bb7c2cf1b40 (patch)
treed5981c213abc0c3a7f056ee4f9e1dce955de13f9 /llvm/lib/CodeGen/StackSlotColoring.cpp
parentd68b2d043865e1c106432f2ab9c1b99a5a2ba86e (diff)
downloadbcm5719-llvm-8d71a757774daf1558086b6133ce4bb7c2cf1b40.tar.gz
bcm5719-llvm-8d71a757774daf1558086b6133ce4bb7c2cf1b40.zip
More refactoring. Move getRegClass from TargetOperandInfo to TargetInstrInfo.
llvm-svn: 133944
Diffstat (limited to 'llvm/lib/CodeGen/StackSlotColoring.cpp')
-rw-r--r--llvm/lib/CodeGen/StackSlotColoring.cpp4
1 files changed, 2 insertions, 2 deletions
diff --git a/llvm/lib/CodeGen/StackSlotColoring.cpp b/llvm/lib/CodeGen/StackSlotColoring.cpp
index 01f5b5627f4..aefaa1098bc 100644
--- a/llvm/lib/CodeGen/StackSlotColoring.cpp
+++ b/llvm/lib/CodeGen/StackSlotColoring.cpp
@@ -521,7 +521,7 @@ bool StackSlotColoring::PropagateBackward(MachineBasicBlock::iterator MII,
if (MO.getSubReg() || MII->isSubregToReg())
return false;
- const TargetRegisterClass *RC = TID.OpInfo[i].getRegClass(TRI);
+ const TargetRegisterClass *RC = TII->getRegClass(TID, i, TRI);
if (RC && !RC->contains(NewReg))
return false;
@@ -583,7 +583,7 @@ bool StackSlotColoring::PropagateForward(MachineBasicBlock::iterator MII,
if (MO.getSubReg())
return false;
- const TargetRegisterClass *RC = TID.OpInfo[i].getRegClass(TRI);
+ const TargetRegisterClass *RC = TII->getRegClass(TID, i, TRI);
if (RC && !RC->contains(NewReg))
return false;
if (MO.isKill())
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