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| author | Stanislav Mekhanoshin <Stanislav.Mekhanoshin@amd.com> | 2017-05-23 19:54:48 +0000 |
|---|---|---|
| committer | Stanislav Mekhanoshin <Stanislav.Mekhanoshin@amd.com> | 2017-05-23 19:54:48 +0000 |
| commit | 53a21292f87d85e9a26c12a53fdbf8b3aeb66cc2 (patch) | |
| tree | 265408298e5da81dca03f5975884818c2a621cd4 /llvm/lib/CodeGen/SlotIndexes.cpp | |
| parent | e6366f505f3db54c7459bab0ff65fd9f5ddbab88 (diff) | |
| download | bcm5719-llvm-53a21292f87d85e9a26c12a53fdbf8b3aeb66cc2.tar.gz bcm5719-llvm-53a21292f87d85e9a26c12a53fdbf8b3aeb66cc2.zip | |
[AMDGPU] Combine and (srl) into shl (bfe)
Perform DAG combine:
and (srl x, c), mask => shl (bfe x, nb + c, mask >> nb), nb
Where nb is a number of trailing zeroes in mask.
It replaces two instructions with two and BFE is generally a more
expensive one. However this is only done if we are selecting a byte
or word at an aligned boundary which results in a proper SDWA
operand pattern. It is only done if SDWA is supported.
TODO: improve SDWA pass to actually convert this pattern. It is not
done now because we have an immediate in the instruction, which has
be moved into a VGPR.
Differential Revision: https://reviews.llvm.org/D33455
llvm-svn: 303681
Diffstat (limited to 'llvm/lib/CodeGen/SlotIndexes.cpp')
0 files changed, 0 insertions, 0 deletions
