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authorSimon Pilgrim <llvm-dev@redking.me.uk>2019-02-08 18:57:38 +0000
committerSimon Pilgrim <llvm-dev@redking.me.uk>2019-02-08 18:57:38 +0000
commiteb6a47a46274378f8665057bf28ec62d266600dc (patch)
tree177041d287b18aebf21341a7cad17281099dbbed /llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
parent01486b22bb62a4020b39001df25442fa2b1d2228 (diff)
downloadbcm5719-llvm-eb6a47a46274378f8665057bf28ec62d266600dc.tar.gz
bcm5719-llvm-eb6a47a46274378f8665057bf28ec62d266600dc.zip
[TargetLowering] Use ISD::FSHR in expandFixedPointMul
Replace OR(SHL,SRL) pattern with ISD::FSHR (legalization expands this later if necessary) - this helps with the scale == 0 'undefined' drop-through case that was discussed on D55720. llvm-svn: 353546
Diffstat (limited to 'llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp')
-rw-r--r--llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp7
1 files changed, 2 insertions, 5 deletions
diff --git a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
index c8b66d05a01..0f343f5989f 100644
--- a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
@@ -5512,9 +5512,6 @@ TargetLowering::expandFixedPointMul(SDNode *Node, SelectionDAG &DAG) const {
// are scaled. The result is given to us in 2 halves, so we only want part of
// both in the result.
EVT ShiftTy = getShiftAmountTy(VT, DAG.getDataLayout());
- Lo = DAG.getNode(ISD::SRL, dl, VT, Lo, DAG.getConstant(Scale, dl, ShiftTy));
- Hi = DAG.getNode(
- ISD::SHL, dl, VT, Hi,
- DAG.getConstant(VT.getScalarSizeInBits() - Scale, dl, ShiftTy));
- return DAG.getNode(ISD::OR, dl, VT, Lo, Hi);
+ return DAG.getNode(ISD::FSHR, dl, VT, Hi, Lo,
+ DAG.getConstant(Scale, dl, ShiftTy));
}
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