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authorEvan Cheng <evan.cheng@apple.com>2006-10-09 20:57:25 +0000
committerEvan Cheng <evan.cheng@apple.com>2006-10-09 20:57:25 +0000
commite71fe34d75f90e3c677fbfa6f8d749f5eb57ebef (patch)
tree102f8962cc2acaf312ba51005835fc3ac769d214 /llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
parent0a2a4b1fbe2ab657279719bcda85cdb3b9923f5c (diff)
downloadbcm5719-llvm-e71fe34d75f90e3c677fbfa6f8d749f5eb57ebef.tar.gz
bcm5719-llvm-e71fe34d75f90e3c677fbfa6f8d749f5eb57ebef.zip
Reflects ISD::LOAD / ISD::LOADX / LoadSDNode changes.
llvm-svn: 30844
Diffstat (limited to 'llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp')
-rw-r--r--llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp21
1 files changed, 12 insertions, 9 deletions
diff --git a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
index 1c00c9136c3..73cefc4e385 100644
--- a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
@@ -552,9 +552,10 @@ bool TargetLowering::SimplifyDemandedBits(SDOperand Op, uint64_t DemandedMask,
KnownOne = 0;
break;
}
- case ISD::LOADX: {
+ case ISD::LOAD: {
if (ISD::isZEXTLoad(Op.Val)) {
- MVT::ValueType VT = cast<VTSDNode>(Op.getOperand(3))->getVT();
+ LoadSDNode *LD = cast<LoadSDNode>(Op);
+ MVT::ValueType VT = LD->getLoadVT();
KnownZero |= ~MVT::getIntVTBitMask(VT) & DemandedMask;
}
break;
@@ -892,9 +893,10 @@ void TargetLowering::ComputeMaskedBits(SDOperand Op, uint64_t Mask,
KnownOne = 0;
return;
}
- case ISD::LOADX: {
+ case ISD::LOAD: {
if (ISD::isZEXTLoad(Op.Val)) {
- MVT::ValueType VT = cast<VTSDNode>(Op.getOperand(3))->getVT();
+ LoadSDNode *LD = cast<LoadSDNode>(Op);
+ MVT::ValueType VT = LD->getLoadVT();
KnownZero |= ~MVT::getIntVTBitMask(VT) & Mask;
}
return;
@@ -1197,15 +1199,16 @@ unsigned TargetLowering::ComputeNumSignBits(SDOperand Op, unsigned Depth) const{
}
// Handle LOADX separately here. EXTLOAD case will fallthrough.
- if (Op.getOpcode() == ISD::LOADX) {
- unsigned LType = Op.getConstantOperandVal(4);
- switch (LType) {
+ if (Op.getOpcode() == ISD::LOAD) {
+ LoadSDNode *LD = cast<LoadSDNode>(Op);
+ unsigned ExtType = LD->getExtensionType();
+ switch (ExtType) {
default: break;
case ISD::SEXTLOAD: // '17' bits known
- Tmp = MVT::getSizeInBits(cast<VTSDNode>(Op.getOperand(3))->getVT());
+ Tmp = MVT::getSizeInBits(LD->getLoadVT());
return VTBits-Tmp+1;
case ISD::ZEXTLOAD: // '16' bits known
- Tmp = MVT::getSizeInBits(cast<VTSDNode>(Op.getOperand(3))->getVT());
+ Tmp = MVT::getSizeInBits(LD->getLoadVT());
return VTBits-Tmp;
}
}
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