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| author | Dan Gohman <gohman@apple.com> | 2010-02-10 16:03:48 +0000 |
|---|---|---|
| committer | Dan Gohman <gohman@apple.com> | 2010-02-10 16:03:48 +0000 |
| commit | 4a618827de7c540c68685789d1eb9b2b50cdc33f (patch) | |
| tree | 0d17edfcf8589f2399f826701396f57fe8f98da8 /llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp | |
| parent | 7bf08432d2c618de728bc7671b8c5360966050bf (diff) | |
| download | bcm5719-llvm-4a618827de7c540c68685789d1eb9b2b50cdc33f.tar.gz bcm5719-llvm-4a618827de7c540c68685789d1eb9b2b50cdc33f.zip | |
Fix "the the" and similar typos.
llvm-svn: 95781
Diffstat (limited to 'llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp')
| -rw-r--r-- | llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp index f923927c43e..d74ec7e2e5d 100644 --- a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp @@ -2366,7 +2366,7 @@ getRegForInlineAsmConstraint(const std::string &Constraint, E = RI->regclass_end(); RCI != E; ++RCI) { const TargetRegisterClass *RC = *RCI; - // If none of the the value types for this register class are valid, we + // If none of the value types for this register class are valid, we // can't use it. For example, 64-bit reg classes on 32-bit targets. bool isLegal = false; for (TargetRegisterClass::vt_iterator I = RC->vt_begin(), E = RC->vt_end(); |
