summaryrefslogtreecommitdiffstats
path: root/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
diff options
context:
space:
mode:
authorSanjay Patel <spatel@rotateright.com>2019-05-14 00:39:40 +0000
committerSanjay Patel <spatel@rotateright.com>2019-05-14 00:39:40 +0000
commit3a13d970aa66ab55707aadfd7b86f32e9139602c (patch)
tree32756d5afa7bd95e27a71e3d6970d6e6e315c08e /llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
parenta2ad7692263a20764bb5eb396a5dd6a748f74579 (diff)
downloadbcm5719-llvm-3a13d970aa66ab55707aadfd7b86f32e9139602c.tar.gz
bcm5719-llvm-3a13d970aa66ab55707aadfd7b86f32e9139602c.zip
[SDAG, x86] allow targets to override test for binop opcodes
This follows the pattern of the existing isCommutativeBinOp(). x86 shows improvements from vector narrowing for the min/max opcodes. llvm-svn: 360639
Diffstat (limited to 'llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp')
-rw-r--r--llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp3
1 files changed, 2 insertions, 1 deletions
diff --git a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
index fe982b1aa96..3f3305f3ab9 100644
--- a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
@@ -1747,8 +1747,9 @@ bool TargetLowering::SimplifyDemandedVectorElts(SDValue Op,
static APInt getKnownUndefForVectorBinop(SDValue BO, SelectionDAG &DAG,
const APInt &UndefOp0,
const APInt &UndefOp1) {
+ const TargetLowering &TLI = DAG.getTargetLoweringInfo();
EVT VT = BO.getValueType();
- assert(ISD::isBinaryOp(BO.getNode()) && VT.isVector() && "Vector binop only");
+ assert(TLI.isBinOp(BO.getOpcode()) && VT.isVector() && "Vector binop only");
EVT EltVT = VT.getVectorElementType();
unsigned NumElts = VT.getVectorNumElements();
OpenPOWER on IntegriCloud