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| author | Dale Johannesen <dalej@apple.com> | 2010-04-20 22:34:09 +0000 |
|---|---|---|
| committer | Dale Johannesen <dalej@apple.com> | 2010-04-20 22:34:09 +0000 |
| commit | 0522b90cdb3eb3564a4ac7a922c7a43fd3c28743 (patch) | |
| tree | d80f0b4673575fa80561133fc6b3ba7ffa01944e /llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp | |
| parent | 2176643241d8272ec1b1ef5c3ce008449ef7fd7d (diff) | |
| download | bcm5719-llvm-0522b90cdb3eb3564a4ac7a922c7a43fd3c28743.tar.gz bcm5719-llvm-0522b90cdb3eb3564a4ac7a922c7a43fd3c28743.zip | |
Because of the EMMS problem, right now we have to support
user-defined operations that use MMX register types, but
the compiler shouldn't generate them on its own. This adds
a Synthesizable abstraction to represent this, and changes
the vector widening computation so it won't produce MMX types.
(The motivation is to remove noise from the ABI compatibility
part of the gcc test suite, which has some breakage right now.)
llvm-svn: 101951
Diffstat (limited to 'llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp')
| -rw-r--r-- | llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp index 11dca398b7c..5c3992ea061 100644 --- a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp @@ -720,7 +720,7 @@ void TargetLowering::computeRegisterProperties() { unsigned NElts = VT.getVectorNumElements(); for (unsigned nVT = i+1; nVT <= MVT::LAST_VECTOR_VALUETYPE; ++nVT) { EVT SVT = (MVT::SimpleValueType)nVT; - if (isTypeLegal(SVT) && SVT.getVectorElementType() == EltVT && + if (isTypeSynthesizable(SVT) && SVT.getVectorElementType() == EltVT && SVT.getVectorNumElements() > NElts && NElts != 1) { TransformToType[i] = SVT; ValueTypeActions.setTypeAction(VT, Promote); |
