summaryrefslogtreecommitdiffstats
path: root/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
diff options
context:
space:
mode:
authorBill Wendling <isanbard@gmail.com>2008-08-22 20:51:05 +0000
committerBill Wendling <isanbard@gmail.com>2008-08-22 20:51:05 +0000
commitfc4f64eed018d60953bb848505f2d9b388e4a3aa (patch)
treeee0707f6aada01ef44838c078fe260f5c224b54b /llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
parent938a77f4c9bee24ecd21b270c6d2e400e64ef1ea (diff)
downloadbcm5719-llvm-fc4f64eed018d60953bb848505f2d9b388e4a3aa.tar.gz
bcm5719-llvm-fc4f64eed018d60953bb848505f2d9b388e4a3aa.zip
Reverting r55190, r55191, and r55192. They broke the build with this error message:
{standard input}:17:bad register name `%sil' make[4]: *** [libgcc/./_addvsi3.o] Error 1 make[4]: *** Waiting for unfinished jobs.... {standard input}:23:bad register name `%dil' {standard input}:28:bad register name `%dil' make[4]: *** [libgcc/./_addvdi3.o] Error 1 {standard input}:18:bad register name `%sil' make[4]: *** [libgcc/./_subvsi3.o] Error 1 llvm-svn: 55200
Diffstat (limited to 'llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp')
-rw-r--r--llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp2
1 files changed, 1 insertions, 1 deletions
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
index e13cfc0fa03..9304c0e7a16 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
@@ -5113,7 +5113,7 @@ void SelectionDAGISel::BuildSelectionDAG(SelectionDAG &DAG, BasicBlock *LLVMBB,
cast<BranchInst>(LLVMBB->getTerminator())->isUnconditional()) {
if (FastISel *F = TLI.createFastISel(FuncInfo.MF)) {
Begin = F->SelectInstructions(Begin, LLVMBB->end(),
- FuncInfo.ValueMap, FuncInfo.MBBMap, BB);
+ FuncInfo.ValueMap, BB);
// Clean up the FastISel object. TODO: Reorganize what data is
// stored in the FastISel class itself and what is merely passed
OpenPOWER on IntegriCloud