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author | Dan Gohman <gohman@apple.com> | 2007-06-13 14:55:16 +0000 |
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committer | Dan Gohman <gohman@apple.com> | 2007-06-13 14:55:16 +0000 |
commit | cbd51c8b60bf73aa17cde37950e0385bc42a28fe (patch) | |
tree | 4e84c1ca8271773ded03b4a488fa3a642f77a237 /llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp | |
parent | 97f7236e70e314c7f87d754d1c1cbd0dfe2cf6e1 (diff) | |
download | bcm5719-llvm-cbd51c8b60bf73aa17cde37950e0385bc42a28fe.tar.gz bcm5719-llvm-cbd51c8b60bf73aa17cde37950e0385bc42a28fe.zip |
When creating CopyFromReg nodes, always use legal types. And use the
correct types for the result vector, even though it is currently bitcasted
to a different type immediately.
llvm-svn: 37568
Diffstat (limited to 'llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp')
-rw-r--r-- | llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp index 72daa66bd57..390429e74f7 100644 --- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp @@ -772,7 +772,7 @@ SDOperand SelectionDAGLowering::getValue(const Value *V) { // If the register was promoted, use TRUNCATE or FP_ROUND as appropriate. for (unsigned i = 0; i != NE; ++i) { SDOperand Op = DAG.getCopyFromReg(DAG.getEntryNode(), InReg++, - PTyElementVT); + PTyLegalElementVT); if (MVT::isFloatingPoint(PTyElementVT)) Op = DAG.getNode(ISD::FP_ROUND, PTyElementVT, Op); else @@ -782,17 +782,17 @@ SDOperand SelectionDAGLowering::getValue(const Value *V) { } else { // If the register was expanded, use BUILD_PAIR. assert((NE & 1) == 0 && "Must expand into a multiple of 2 elements!"); - for (unsigned i = 0; i != NE/2; ++i) { + for (unsigned i = 0; i != NE; ++i) { SDOperand Op0 = DAG.getCopyFromReg(DAG.getEntryNode(), InReg++, - PTyElementVT); + PTyLegalElementVT); SDOperand Op1 = DAG.getCopyFromReg(DAG.getEntryNode(), InReg++, - PTyElementVT); - Ops.push_back(DAG.getNode(ISD::BUILD_PAIR, VT, Op0, Op1)); + PTyLegalElementVT); + Ops.push_back(DAG.getNode(ISD::BUILD_PAIR, PTyElementVT, Op0, Op1)); } } Ops.push_back(DAG.getConstant(NE, MVT::i32)); - Ops.push_back(DAG.getValueType(PTyLegalElementVT)); + Ops.push_back(DAG.getValueType(PTyElementVT)); N = DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, &Ops[0], Ops.size()); // Finally, use a VBIT_CONVERT to make this available as the appropriate |