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authorReid Spencer <rspencer@reidspencer.com>2006-01-16 21:12:35 +0000
committerReid Spencer <rspencer@reidspencer.com>2006-01-16 21:12:35 +0000
commitb4f9a6f110ff455eaa3538275dcdbac0553031d4 (patch)
tree5c5b78085c246bceae041a795428b7aa0718b0fd /llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
parent84c00ea718b269d245dbf8921061537a25f3ba9e (diff)
downloadbcm5719-llvm-b4f9a6f110ff455eaa3538275dcdbac0553031d4.tar.gz
bcm5719-llvm-b4f9a6f110ff455eaa3538275dcdbac0553031d4.zip
For PR411:
This patch is an incremental step towards supporting a flat symbol table. It de-overloads the intrinsic functions by providing type-specific intrinsics and arranging for automatically upgrading from the old overloaded name to the new non-overloaded name. Specifically: llvm.isunordered -> llvm.isunordered.f32, llvm.isunordered.f64 llvm.sqrt -> llvm.sqrt.f32, llvm.sqrt.f64 llvm.ctpop -> llvm.ctpop.i8, llvm.ctpop.i16, llvm.ctpop.i32, llvm.ctpop.i64 llvm.ctlz -> llvm.ctlz.i8, llvm.ctlz.i16, llvm.ctlz.i32, llvm.ctlz.i64 llvm.cttz -> llvm.cttz.i8, llvm.cttz.i16, llvm.cttz.i32, llvm.cttz.i64 New code should not use the overloaded intrinsic names. Warnings will be emitted if they are used. llvm-svn: 25366
Diffstat (limited to 'llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp')
-rw-r--r--llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp21
1 files changed, 16 insertions, 5 deletions
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
index 31b7fc7b6ef..cd4250b48b3 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
@@ -963,12 +963,14 @@ SelectionDAGLowering::visitIntrinsicCall(CallInst &I, unsigned Intrinsic) {
setValue(&I, DAG.getNode(ISD::UNDEF, TLI.getValueType(I.getType())));
return 0;
- case Intrinsic::isunordered:
+ case Intrinsic::isunordered_f32:
+ case Intrinsic::isunordered_f64:
setValue(&I, DAG.getSetCC(MVT::i1,getValue(I.getOperand(1)),
getValue(I.getOperand(2)), ISD::SETUO));
return 0;
- case Intrinsic::sqrt:
+ case Intrinsic::sqrt_f32:
+ case Intrinsic::sqrt_f64:
setValue(&I, DAG.getNode(ISD::FSQRT,
getValue(I.getOperand(1)).getValueType(),
getValue(I.getOperand(1))));
@@ -996,17 +998,26 @@ SelectionDAGLowering::visitIntrinsicCall(CallInst &I, unsigned Intrinsic) {
getValue(I.getOperand(1)).getValueType(),
getValue(I.getOperand(1))));
return 0;
- case Intrinsic::cttz:
+ case Intrinsic::cttz_i8:
+ case Intrinsic::cttz_i16:
+ case Intrinsic::cttz_i32:
+ case Intrinsic::cttz_i64:
setValue(&I, DAG.getNode(ISD::CTTZ,
getValue(I.getOperand(1)).getValueType(),
getValue(I.getOperand(1))));
return 0;
- case Intrinsic::ctlz:
+ case Intrinsic::ctlz_i8:
+ case Intrinsic::ctlz_i16:
+ case Intrinsic::ctlz_i32:
+ case Intrinsic::ctlz_i64:
setValue(&I, DAG.getNode(ISD::CTLZ,
getValue(I.getOperand(1)).getValueType(),
getValue(I.getOperand(1))));
return 0;
- case Intrinsic::ctpop:
+ case Intrinsic::ctpop_i8:
+ case Intrinsic::ctpop_i16:
+ case Intrinsic::ctpop_i32:
+ case Intrinsic::ctpop_i64:
setValue(&I, DAG.getNode(ISD::CTPOP,
getValue(I.getOperand(1)).getValueType(),
getValue(I.getOperand(1))));
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