Merge information about the number of zero, one, and sign bits of live-out

registers at phis. This enables us to eliminate a lot of pointless zexts during
the DAGCombine phase. This fixes <rdar://problem/8760114>.

llvm-svn: 126380

1 files changed, 6 insertions, 1 deletions

diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
index d5400630835..68ba966d268 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
@@ -842,7 +842,12 @@ void SelectionDAGISel::SelectAllBasicBlocks(const Function &Fn) {
         }
       }
 
-      if (!AllPredsVisited) {
+      if (AllPredsVisited) {
+        for (BasicBlock::const_iterator I = LLVMBB->begin(), E = LLVMBB->end();
+             I != E && isa<PHINode>(I); ++I) {
+          FuncInfo->ComputePHILiveOutRegInfo(cast<PHINode>(I));
+        }
+      } else {
         for (BasicBlock::const_iterator I = LLVMBB->begin(), E = LLVMBB->end();
              I != E && isa<PHINode>(I); ++I) {
           FuncInfo->InvalidatePHILiveOutRegInfo(cast<PHINode>(I));