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| author | Dan Gohman <gohman@apple.com> | 2008-02-10 18:45:23 +0000 |
|---|---|---|
| committer | Dan Gohman <gohman@apple.com> | 2008-02-10 18:45:23 +0000 |
| commit | 3a4be0fdefc64931e6ae95165c529a916e4dd32d (patch) | |
| tree | 9ffd3d1f95550f841f32371fb7ec29de8d2e0ed5 /llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp | |
| parent | 60fb1d80fe7d72057737e9b81049efbc78244207 (diff) | |
| download | bcm5719-llvm-3a4be0fdefc64931e6ae95165c529a916e4dd32d.tar.gz bcm5719-llvm-3a4be0fdefc64931e6ae95165c529a916e4dd32d.zip | |
Rename MRegisterInfo to TargetRegisterInfo.
llvm-svn: 46930
Diffstat (limited to 'llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp')
| -rw-r--r-- | llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp | 13 |
1 files changed, 7 insertions, 6 deletions
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp index 55231f34a1b..9e91e9f2081 100644 --- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp @@ -35,7 +35,7 @@ #include "llvm/CodeGen/MachineRegisterInfo.h" #include "llvm/CodeGen/SchedulerRegistry.h" #include "llvm/CodeGen/SelectionDAG.h" -#include "llvm/Target/MRegisterInfo.h" +#include "llvm/Target/TargetRegisterInfo.h" #include "llvm/Target/TargetData.h" #include "llvm/Target/TargetFrameInfo.h" #include "llvm/Target/TargetInstrInfo.h" @@ -3148,11 +3148,12 @@ void RegsForValue::AddInlineAsmOperands(unsigned Code, SelectionDAG &DAG, /// register class for the register. Otherwise, return null. static const TargetRegisterClass * isAllocatableRegister(unsigned Reg, MachineFunction &MF, - const TargetLowering &TLI, const MRegisterInfo *MRI) { + const TargetLowering &TLI, + const TargetRegisterInfo *TRI) { MVT::ValueType FoundVT = MVT::Other; const TargetRegisterClass *FoundRC = 0; - for (MRegisterInfo::regclass_iterator RCI = MRI->regclass_begin(), - E = MRI->regclass_end(); RCI != E; ++RCI) { + for (TargetRegisterInfo::regclass_iterator RCI = TRI->regclass_begin(), + E = TRI->regclass_end(); RCI != E; ++RCI) { MVT::ValueType ThisVT = MVT::Other; const TargetRegisterClass *RC = *RCI; @@ -3416,7 +3417,7 @@ GetRegistersForValue(AsmOperandInfo &OpInfo, bool HasEarlyClobber, OpInfo.ConstraintVT); } - const MRegisterInfo *MRI = DAG.getTarget().getRegisterInfo(); + const TargetRegisterInfo *TRI = DAG.getTarget().getRegisterInfo(); unsigned NumAllocated = 0; for (unsigned i = 0, e = RegClassRegs.size(); i != e; ++i) { unsigned Reg = RegClassRegs[i]; @@ -3431,7 +3432,7 @@ GetRegistersForValue(AsmOperandInfo &OpInfo, bool HasEarlyClobber, // Check to see if this register is allocatable (i.e. don't give out the // stack pointer). if (RC == 0) { - RC = isAllocatableRegister(Reg, MF, TLI, MRI); + RC = isAllocatableRegister(Reg, MF, TLI, TRI); if (!RC) { // Couldn't allocate this register. // Reset NumAllocated to make sure we return consecutive registers. NumAllocated = 0; |

