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authorChris Lattner <sabre@nondot.org>2007-02-14 07:18:16 +0000
committerChris Lattner <sabre@nondot.org>2007-02-14 07:18:16 +0000
commit1cf84d27451c5eb87b06aaf8e21529326de92956 (patch)
treef38971caedec74907338190ef5067d5e8fa8470a /llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
parent4da5e17cfc5befdfc6f77df2ed8cd3266b73b0e0 (diff)
downloadbcm5719-llvm-1cf84d27451c5eb87b06aaf8e21529326de92956.tar.gz
bcm5719-llvm-1cf84d27451c5eb87b06aaf8e21529326de92956.zip
Refix CodeGen/Generic/switch-lower.ll. In contrast to my previous patch,
this doesn't miscompile lots of programs :) llvm-svn: 34268
Diffstat (limited to 'llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp')
-rw-r--r--llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp10
1 files changed, 5 insertions, 5 deletions
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
index e72d88c7340..0192c287cd1 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
@@ -1205,8 +1205,8 @@ void SelectionDAGLowering::visitSwitch(SwitchInst &I) {
if ((TLI.isOperationLegal(ISD::BR_JT, MVT::Other) ||
TLI.isOperationLegal(ISD::BRIND, MVT::Other)) &&
Cases.size() > 5) {
- uint64_t First =cast<ConstantInt>(Cases.front().first)->getZExtValue();
- uint64_t Last = cast<ConstantInt>(Cases.back().first)->getZExtValue();
+ uint64_t First =cast<ConstantInt>(Cases.front().first)->getSExtValue();
+ uint64_t Last = cast<ConstantInt>(Cases.back().first)->getSExtValue();
double Density = (double)Cases.size() / (double)((Last - First) + 1ULL);
if (Density >= 0.3125) {
@@ -1255,7 +1255,7 @@ void SelectionDAGLowering::visitSwitch(SwitchInst &I) {
std::vector<MachineBasicBlock*> DestBBs;
uint64_t TEI = First;
for (CaseItr ii = Cases.begin(), ee = Cases.end(); ii != ee; ++TEI)
- if (cast<ConstantInt>(ii->first)->getZExtValue() == TEI) {
+ if (cast<ConstantInt>(ii->first)->getSExtValue() == TEI) {
DestBBs.push_back(ii->second);
++ii;
} else {
@@ -1363,8 +1363,8 @@ void SelectionDAGLowering::visitSwitch(SwitchInst &I) {
// Create a CaseBlock record representing a conditional branch to
// the LHS node if the value being switched on SV is less than C.
// Otherwise, branch to LHS.
- ISD::CondCode CC = ISD::SETLT;
- SelectionDAGISel::CaseBlock CB(CC, SV, C, TrueBB, FalseBB, CR.CaseBB);
+ SelectionDAGISel::CaseBlock CB(ISD::SETLT, SV, C, TrueBB, FalseBB,
+ CR.CaseBB);
if (CR.CaseBB == CurMBB)
visitSwitchCase(CB);
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