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authorAnton Korobeynikov <asl@math.spbu.ru>2007-05-02 22:15:48 +0000
committerAnton Korobeynikov <asl@math.spbu.ru>2007-05-02 22:15:48 +0000
commit11940fbba378fc6623d323274140cd0972c32164 (patch)
tree50f4961d18c3248a5991440a3ddfa54aa31e9e56 /llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
parentba3b7ee03033c5569f20a8697e11eff61b587f39 (diff)
downloadbcm5719-llvm-11940fbba378fc6623d323274140cd0972c32164.tar.gz
bcm5719-llvm-11940fbba378fc6623d323274140cd0972c32164.zip
Properly set arguments bitwidth of EHSELECT node
llvm-svn: 36654
Diffstat (limited to 'llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp')
-rw-r--r--llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp4
1 files changed, 2 insertions, 2 deletions
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
index 3f6a10ae44f..8bd6c97e32c 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
@@ -2632,7 +2632,7 @@ SelectionDAGLowering::visitIntrinsicCall(CallInst &I, unsigned Intrinsic) {
if (Reg) CurMBB->addLiveIn(Reg);
// Insert the EHSELECTION instruction.
- SDVTList VTs = DAG.getVTList(MVT::i32, MVT::Other);
+ SDVTList VTs = DAG.getVTList(TLI.getPointerTy(), MVT::Other);
SDOperand Ops[2];
Ops[0] = getValue(I.getOperand(1));
Ops[1] = getRoot();
@@ -2640,7 +2640,7 @@ SelectionDAGLowering::visitIntrinsicCall(CallInst &I, unsigned Intrinsic) {
setValue(&I, Op);
DAG.setRoot(Op.getValue(1));
} else {
- setValue(&I, DAG.getConstant(0, MVT::i32));
+ setValue(&I, DAG.getConstant(0, TLI.getPointerTy()));
}
return 0;
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