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authorBob Wilson <bob.wilson@apple.com>2015-09-18 05:36:13 +0000
committerBob Wilson <bob.wilson@apple.com>2015-09-18 05:36:13 +0000
commitdd0eadce7d4d550d3769fdac60c364b2257ab6c8 (patch)
treebdaafa2a03463a1c31ba49e60a4a8e06074734d5 /llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
parent630dd7ff3584931f8826247c8c35f31f50385906 (diff)
downloadbcm5719-llvm-dd0eadce7d4d550d3769fdac60c364b2257ab6c8.tar.gz
bcm5719-llvm-dd0eadce7d4d550d3769fdac60c364b2257ab6c8.zip
Whitespace. Indent with spaces instead of a tab.
llvm-svn: 247969
Diffstat (limited to 'llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp')
-rw-r--r--llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp2
1 files changed, 1 insertions, 1 deletions
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
index 36c6b90f6e5..44f222aeafd 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
@@ -6133,7 +6133,7 @@ void SelectionDAGBuilder::visitInlineAsm(ImmutableCallSite CS) {
SDISelAsmOperandInfo &Input = ConstraintOperands[OpInfo.MatchingInput];
if (OpInfo.ConstraintVT != Input.ConstraintVT) {
- const TargetRegisterInfo *TRI = DAG.getSubtarget().getRegisterInfo();
+ const TargetRegisterInfo *TRI = DAG.getSubtarget().getRegisterInfo();
std::pair<unsigned, const TargetRegisterClass *> MatchRC =
TLI.getRegForInlineAsmConstraint(TRI, OpInfo.ConstraintCode,
OpInfo.ConstraintVT);
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