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authorMatt Arsenault <Matthew.Arsenault@amd.com>2019-02-22 03:38:47 +0000
committerMatt Arsenault <Matthew.Arsenault@amd.com>2019-02-22 03:38:47 +0000
commit0280a5e143646216ad2040fb2836e7600327eaa2 (patch)
tree9903ded69711de1175f5c017c92643d31d041067 /llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
parent3a391fc0e8eabb3081e8a725c9adfefac6ec4d2e (diff)
downloadbcm5719-llvm-0280a5e143646216ad2040fb2836e7600327eaa2.tar.gz
bcm5719-llvm-0280a5e143646216ad2040fb2836e7600327eaa2.zip
DAG: Add helper for creating shifts with correct type
llvm-svn: 354649
Diffstat (limited to 'llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp')
-rw-r--r--llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp3
1 files changed, 2 insertions, 1 deletions
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
index 1b75dc7d2e5..95343f0eae1 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
@@ -573,7 +573,8 @@ static void getCopyToParts(SelectionDAG &DAG, const SDLoc &DL, SDValue Val,
unsigned RoundBits = RoundParts * PartBits;
unsigned OddParts = NumParts - RoundParts;
SDValue OddVal = DAG.getNode(ISD::SRL, DL, ValueVT, Val,
- DAG.getIntPtrConstant(RoundBits, DL));
+ DAG.getShiftAmountConstant(RoundBits, ValueVT, DL, /*LegalTypes*/false));
+
getCopyToParts(DAG, DL, OddVal, Parts + RoundParts, OddParts, PartVT, V,
CallConv);
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