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author | Craig Topper <craig.topper@intel.com> | 2017-12-03 03:07:09 +0000 |
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committer | Craig Topper <craig.topper@intel.com> | 2017-12-03 03:07:09 +0000 |
commit | f3470e1ed4f6322711f6fc059b834d2ce0094c2b (patch) | |
tree | 2000f01b129894f9e1f7b503af43e5c5047b90c6 /llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp | |
parent | 4b27c0554ccdb0c8a380c9b2a9d242674cf66601 (diff) | |
download | bcm5719-llvm-f3470e1ed4f6322711f6fc059b834d2ce0094c2b.tar.gz bcm5719-llvm-f3470e1ed4f6322711f6fc059b834d2ce0094c2b.zip |
[SelectionDAG] Use the inlined APInt shift methods since we've already bounds checked the shift.
The version that takes APInt is out of line. The 'unsigned' version optimizes for the common case of single word APInts.
llvm-svn: 319628
Diffstat (limited to 'llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp')
-rw-r--r-- | llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp | 19 |
1 files changed, 11 insertions, 8 deletions
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp index b456b74abd3..0b59af2fa10 100644 --- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp @@ -2463,27 +2463,30 @@ void SelectionDAG::computeKnownBits(SDValue Op, KnownBits &Known, case ISD::SHL: if (const APInt *ShAmt = getValidShiftAmountConstant(Op)) { computeKnownBits(Op.getOperand(0), Known, DemandedElts, Depth + 1); - Known.Zero <<= *ShAmt; - Known.One <<= *ShAmt; + unsigned Shift = ShAmt->getZExtValue(); + Known.Zero <<= Shift; + Known.One <<= Shift; // Low bits are known zero. - Known.Zero.setLowBits(ShAmt->getZExtValue()); + Known.Zero.setLowBits(Shift); } break; case ISD::SRL: if (const APInt *ShAmt = getValidShiftAmountConstant(Op)) { computeKnownBits(Op.getOperand(0), Known, DemandedElts, Depth + 1); - Known.Zero.lshrInPlace(*ShAmt); - Known.One.lshrInPlace(*ShAmt); + unsigned Shift = ShAmt->getZExtValue(); + Known.Zero.lshrInPlace(Shift); + Known.One.lshrInPlace(Shift); // High bits are known zero. - Known.Zero.setHighBits(ShAmt->getZExtValue()); + Known.Zero.setHighBits(Shift); } break; case ISD::SRA: if (const APInt *ShAmt = getValidShiftAmountConstant(Op)) { computeKnownBits(Op.getOperand(0), Known, DemandedElts, Depth + 1); + unsigned Shift = ShAmt->getZExtValue(); // Sign extend known zero/one bit (else is unknown). - Known.Zero.ashrInPlace(*ShAmt); - Known.One.ashrInPlace(*ShAmt); + Known.Zero.ashrInPlace(Shift); + Known.One.ashrInPlace(Shift); } break; case ISD::SIGN_EXTEND_INREG: { |