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| author | Jeff Cohen <jeffc@jolt-lang.org> | 2005-08-19 04:39:48 +0000 |
|---|---|---|
| committer | Jeff Cohen <jeffc@jolt-lang.org> | 2005-08-19 04:39:48 +0000 |
| commit | d1f22b12822a4c2ec327bad3e728a300841b65f9 (patch) | |
| tree | 1d95d442334e556d4e54724f36d77ad28ff65a7b /llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp | |
| parent | ce400dac21ac4f44d54a7042bc0d6c132cfdef39 (diff) | |
| download | bcm5719-llvm-d1f22b12822a4c2ec327bad3e728a300841b65f9.tar.gz bcm5719-llvm-d1f22b12822a4c2ec327bad3e728a300841b65f9.zip | |
Fix VC++ precedence warning.
llvm-svn: 22902
Diffstat (limited to 'llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp')
| -rw-r--r-- | llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp index 7f0725efaab..8fb6070e94d 100644 --- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp @@ -1171,7 +1171,7 @@ SDOperand SelectionDAG::getNode(unsigned Opcode, MVT::ValueType VT, if (Opcode == ISD::SRA) { // If the sign bit is known to be zero, switch this to a SRL. if (MaskedValueIsZero(N1, - 1ULL << MVT::getSizeInBits(N1.getValueType())-1, + 1ULL << (MVT::getSizeInBits(N1.getValueType())-1), TLI)) return getNode(ISD::SRL, N1.getValueType(), N1, N2); } else { |
