[SelectionDAG] ComputeKnownBits - minimum leading/trailing zero bits in LSHR/SHL (PR44526)

As detailed in https://blog.regehr.org/archives/1709 we don't make use of the known leading/trailing zeros for shifted values in cases where we don't know the shift amount value.

This patch adds support to SelectionDAG::ComputeKnownBits to use KnownBits::countMinTrailingZeros and countMinLeadingZeros to set the minimum guaranteed leading/trailing known zero bits.

Differential Revision: https://reviews.llvm.org/D72573

1 files changed, 11 insertions, 0 deletions

diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
index 1e5e0724f08..4fa438a2795 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
@@ -2834,6 +2834,12 @@ KnownBits SelectionDAG::computeKnownBits(SDValue Op, const APInt &DemandedElts,
       Known.One <<= Shift;
       // Low bits are known zero.
       Known.Zero.setLowBits(Shift);
+    } else {
+      // No matter the shift amount, the trailing zeros will stay zero.
+      Known = computeKnownBits(Op.getOperand(0), DemandedElts, Depth + 1);
+      Known.Zero =
+          APInt::getLowBitsSet(BitWidth, Known.countMinTrailingZeros());
+      Known.One.clearAllBits();
     }
     break;
   case ISD::SRL:
@@ -2847,6 +2853,11 @@ KnownBits SelectionDAG::computeKnownBits(SDValue Op, const APInt &DemandedElts,
     } else if (const APInt *ShMinAmt = getValidMinimumShiftAmountConstant(Op)) {
       // Minimum shift high bits are known zero.
       Known.Zero.setHighBits(ShMinAmt->getZExtValue());
+    } else {
+      // No matter the shift amount, the leading zeros will stay zero.
+      Known = computeKnownBits(Op.getOperand(0), DemandedElts, Depth + 1);
+      Known.Zero = APInt::getHighBitsSet(BitWidth, Known.countMinLeadingZeros());
+      Known.One.clearAllBits();
     }
     break;
   case ISD::SRA: