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authorNadav Rotem <nadav.rotem@intel.com>2012-07-16 18:34:53 +0000
committerNadav Rotem <nadav.rotem@intel.com>2012-07-16 18:34:53 +0000
commit839a06e9d751654fc5e5b2e0050735dd8dff39e5 (patch)
tree53954884da320a4e4bdc0d8b0dfd572f23a477c4 /llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
parentf2bc464f37d61630df971690ae775793d09a03cf (diff)
downloadbcm5719-llvm-839a06e9d751654fc5e5b2e0050735dd8dff39e5.tar.gz
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Make ComputeDemandedBits return a deterministic result when computing an AssertZext value.
In the added testcase the constant 55 was behind an AssertZext of type i1, and ComputeDemandedBits reported that some of the bits were both known to be one and known to be zero. Together with Michael Kuperstein <michael.m.kuperstein@intel.com> llvm-svn: 160305
Diffstat (limited to 'llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp')
-rw-r--r--llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp1
1 files changed, 1 insertions, 0 deletions
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
index 3947648e6a7..cfe71708fe0 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
@@ -1965,6 +1965,7 @@ void SelectionDAG::ComputeMaskedBits(SDValue Op, APInt &KnownZero,
APInt InMask = APInt::getLowBitsSet(BitWidth, VT.getSizeInBits());
ComputeMaskedBits(Op.getOperand(0), KnownZero, KnownOne, Depth+1);
KnownZero |= (~InMask);
+ KnownOne &= (~KnownZero);
return;
}
case ISD::FGETSIGN:
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