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| author | Craig Topper <craig.topper@intel.com> | 2017-12-15 01:03:43 +0000 |
|---|---|---|
| committer | Craig Topper <craig.topper@intel.com> | 2017-12-15 01:03:43 +0000 |
| commit | 5ebf3ac9c2417d4cef0e9e3f86372ee40290b73e (patch) | |
| tree | 8d477ee9f10d5807ad07f85fa425655664517db8 /llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp | |
| parent | 07a28f777eedf011372c4d5d77d44060ec2114c3 (diff) | |
| download | bcm5719-llvm-5ebf3ac9c2417d4cef0e9e3f86372ee40290b73e.tar.gz bcm5719-llvm-5ebf3ac9c2417d4cef0e9e3f86372ee40290b73e.zip | |
[X86] Further rearrange the setOperationAction calls to separate the ones that require 512-bit registers OR VLX into separate sections. NFCI
We have several instructions that were introduced in AVX512F that are only available in 512-bit form on KNL. We still make use of them for 128/256 by artificially widening and extracting during isel.
This commit separates these operations from the true 512-bit operations. This way we can qualify the normal 512-bit operations with needing 512-bit register support. And these special operations will get qualified with needing 512-bit registers OR VLX.
The 512-bit register qualification will be introduced in a future patch this just gets everything grouped to minimize deltas on that patch.
llvm-svn: 320782
Diffstat (limited to 'llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp')
0 files changed, 0 insertions, 0 deletions
