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authorChris Lattner <sabre@nondot.org>2005-10-09 22:12:36 +0000
committerChris Lattner <sabre@nondot.org>2005-10-09 22:12:36 +0000
commit1d3dc006744f4bb44ef913797d3a8e3b514db2ce (patch)
tree2a61daf503f688204c39a644870913cf565e1450 /llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
parent03b9eb506cd03273010f78b9b03117a3fd538e7e (diff)
downloadbcm5719-llvm-1d3dc006744f4bb44ef913797d3a8e3b514db2ce.tar.gz
bcm5719-llvm-1d3dc006744f4bb44ef913797d3a8e3b514db2ce.zip
(X & Y) & C == 0 if either X&C or Y&C are zero
llvm-svn: 23678
Diffstat (limited to 'llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp')
-rw-r--r--llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp8
1 files changed, 6 insertions, 2 deletions
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
index 9a69fdc5fca..b0206a9dcb5 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
@@ -608,11 +608,15 @@ static bool MaskedValueIsZero(const SDOperand &Op, uint64_t Mask,
SrcBits = MVT::getSizeInBits(cast<VTSDNode>(Op.getOperand(1))->getVT());
return (Mask & ((1ULL << SrcBits)-1)) == 0; // Returning only the zext bits.
case ISD::AND:
+ // If either of the operands has zero bits, the result will too.
+ if (MaskedValueIsZero(Op.getOperand(1), Mask, TLI) ||
+ MaskedValueIsZero(Op.getOperand(0), Mask, TLI))
+ return true;
+
// (X & C1) & C2 == 0 iff C1 & C2 == 0.
if (ConstantSDNode *AndRHS = dyn_cast<ConstantSDNode>(Op.getOperand(1)))
return MaskedValueIsZero(Op.getOperand(0),AndRHS->getValue() & Mask, TLI);
-
- // FALL THROUGH
+ return false;
case ISD::OR:
case ISD::XOR:
return MaskedValueIsZero(Op.getOperand(0), Mask, TLI) &&
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