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| author | Andrew Trick <atrick@apple.com> | 2011-06-15 17:16:12 +0000 |
|---|---|---|
| committer | Andrew Trick <atrick@apple.com> | 2011-06-15 17:16:12 +0000 |
| commit | 3013b6ae4ac3a6a141483fd5af7b0995ffb8dcec (patch) | |
| tree | 1bf327d788e68530283c28edea176108273b4e06 /llvm/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp | |
| parent | 19a1f425a7f122f5c1734e213d8f7c90a13c68bb (diff) | |
| download | bcm5719-llvm-3013b6ae4ac3a6a141483fd5af7b0995ffb8dcec.tar.gz bcm5719-llvm-3013b6ae4ac3a6a141483fd5af7b0995ffb8dcec.zip | |
Added -stress-sched flag in the Asserts build.
Added a test case for handling physreg aliases during pre-RA-sched.
llvm-svn: 133063
Diffstat (limited to 'llvm/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp')
| -rw-r--r-- | llvm/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp b/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp index 9f2f0121a86..0d656efb37d 100644 --- a/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp @@ -435,7 +435,7 @@ void ScheduleDAGSDNodes::AddSchedEdges() { // it requires a cross class copy (cost < 0). That means we are only // treating "expensive to copy" register dependency as physical register // dependency. This may change in the future though. - if (Cost >= 0) + if (Cost >= 0 && !StressSched) PhysReg = 0; // If this is a ctrl dep, latency is 1. |
