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authorCraig Topper <craig.topper@gmail.com>2012-03-08 08:22:45 +0000
committerCraig Topper <craig.topper@gmail.com>2012-03-08 08:22:45 +0000
commit5a4bcc749acae6b92451cc9c2aa502d25600fbce (patch)
tree455e4ecf98ac8da6999732b1fe6963dc25d41079 /llvm/lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp
parent544637937af1cee7b301212eb396c2ff8a4b906f (diff)
downloadbcm5719-llvm-5a4bcc749acae6b92451cc9c2aa502d25600fbce.tar.gz
bcm5719-llvm-5a4bcc749acae6b92451cc9c2aa502d25600fbce.zip
Use uint16_t to store instruction implicit uses and defs. Reduces static data.
llvm-svn: 152301
Diffstat (limited to 'llvm/lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp')
-rw-r--r--llvm/lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp4
1 files changed, 2 insertions, 2 deletions
diff --git a/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp b/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp
index 2a5b6ef1be2..24da432a47a 100644
--- a/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp
@@ -425,7 +425,7 @@ static EVT getPhysicalRegisterVT(SDNode *N, unsigned Reg,
const MCInstrDesc &MCID = TII->get(N->getMachineOpcode());
assert(MCID.ImplicitDefs && "Physical reg def must be in implicit def list!");
unsigned NumRes = MCID.getNumDefs();
- for (const unsigned *ImpDef = MCID.getImplicitDefs(); *ImpDef; ++ImpDef) {
+ for (const uint16_t *ImpDef = MCID.getImplicitDefs(); *ImpDef; ++ImpDef) {
if (Reg == *ImpDef)
break;
++NumRes;
@@ -508,7 +508,7 @@ bool ScheduleDAGFast::DelayForLiveRegsBottomUp(SUnit *SU,
const MCInstrDesc &MCID = TII->get(Node->getMachineOpcode());
if (!MCID.ImplicitDefs)
continue;
- for (const unsigned *Reg = MCID.ImplicitDefs; *Reg; ++Reg) {
+ for (const uint16_t *Reg = MCID.getImplicitDefs(); *Reg; ++Reg) {
CheckForLiveRegDef(SU, *Reg, LiveRegDefs, RegAdded, LRegs, TRI);
}
}
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