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| author | Andrew Lenharth <andrewl@lenharth.org> | 2008-06-14 05:48:15 +0000 |
|---|---|---|
| committer | Andrew Lenharth <andrewl@lenharth.org> | 2008-06-14 05:48:15 +0000 |
| commit | f88d50bfccf06b9032e4e5b4d4a2af5b91540348 (patch) | |
| tree | 9c31fc750337042a4f0d921691534dc4aa4a1060 /llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp | |
| parent | a88cd4ea2a205346302760b5f0c8b815a1c20c16 (diff) | |
| download | bcm5719-llvm-f88d50bfccf06b9032e4e5b4d4a2af5b91540348.tar.gz bcm5719-llvm-f88d50bfccf06b9032e4e5b4d4a2af5b91540348.zip | |
add missing atomic intrinsic from gcc
llvm-svn: 52270
Diffstat (limited to 'llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp')
| -rw-r--r-- | llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp index dd5a350f49d..87bb1dbf142 100644 --- a/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp @@ -1254,6 +1254,7 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) { case ISD::ATOMIC_LOAD_AND: case ISD::ATOMIC_LOAD_OR: case ISD::ATOMIC_LOAD_XOR: + case ISD::ATOMIC_LOAD_NAND: case ISD::ATOMIC_LOAD_MIN: case ISD::ATOMIC_LOAD_MAX: case ISD::ATOMIC_LOAD_UMIN: @@ -4285,6 +4286,7 @@ SDOperand SelectionDAGLegalize::PromoteOp(SDOperand Op) { case ISD::ATOMIC_LOAD_AND: case ISD::ATOMIC_LOAD_OR: case ISD::ATOMIC_LOAD_XOR: + case ISD::ATOMIC_LOAD_NAND: case ISD::ATOMIC_LOAD_MIN: case ISD::ATOMIC_LOAD_MAX: case ISD::ATOMIC_LOAD_UMIN: |
