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author | Andrew Lenharth <andrewl@lenharth.org> | 2005-12-24 23:42:32 +0000 |
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committer | Andrew Lenharth <andrewl@lenharth.org> | 2005-12-24 23:42:32 +0000 |
commit | 7259426d88b1e07533312b822fb7c58029400f56 (patch) | |
tree | f15bf8b1250c80a11b99f832751fb4631ec7d312 /llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp | |
parent | 0dc12c38e5336083af50d4d22f901c241828e628 (diff) | |
download | bcm5719-llvm-7259426d88b1e07533312b822fb7c58029400f56.tar.gz bcm5719-llvm-7259426d88b1e07533312b822fb7c58029400f56.zip |
Support Custom lowering of a few more operations.
Alpha needs to custom lower *DIV and *REM
llvm-svn: 25006
Diffstat (limited to 'llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp')
-rw-r--r-- | llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp | 36 |
1 files changed, 31 insertions, 5 deletions
diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp index af1d47697a5..1d684191219 100644 --- a/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp @@ -537,6 +537,7 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) { case ISD::GlobalAddress: case ISD::TargetGlobalAddress: case ISD::ExternalSymbol: + case ISD::TargetExternalSymbol: case ISD::ConstantPool: // Nothing to do. case ISD::BasicBlock: case ISD::CONDCODE: @@ -1954,9 +1955,25 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) { Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the RHS. break; } - if (Tmp1 != Node->getOperand(0) || - Tmp2 != Node->getOperand(1)) - Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1,Tmp2); + switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) { + case TargetLowering::Legal: + if (Tmp1 != Node->getOperand(0) || + Tmp2 != Node->getOperand(1)) + Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1,Tmp2); + break; + case TargetLowering::Custom: { + Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1, Tmp2); + SDOperand Tmp = TLI.LowerOperation(Result, DAG); + if (Tmp.Val) { + Tmp = LegalizeOp(Tmp); // Relegalize input. + AddLegalizedOperand(Op, Tmp); + return Tmp; + } + break; + } + default: + assert(0 && "Operation not supported"); + } break; case ISD::BUILD_PAIR: { @@ -1997,8 +2014,17 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) { Tmp2); break; case TargetLowering::Promote: - case TargetLowering::Custom: - assert(0 && "Cannot promote/custom handle this yet!"); + assert(0 && "Cannot promote handle this yet!"); + case TargetLowering::Custom: { + Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1, Tmp2); + SDOperand Tmp = TLI.LowerOperation(Result, DAG); + if (Tmp.Val) { + Tmp = LegalizeOp(Tmp); // Relegalize input. + AddLegalizedOperand(Op, Tmp); + return Tmp; + } + break; + } case TargetLowering::Expand: if (MVT::isInteger(Node->getValueType(0))) { MVT::ValueType VT = Node->getValueType(0); |