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| author | Alexander Timofeev <Alexander.Timofeev@amd.com> | 2019-05-26 20:33:26 +0000 |
|---|---|---|
| committer | Alexander Timofeev <Alexander.Timofeev@amd.com> | 2019-05-26 20:33:26 +0000 |
| commit | ba447bae7448435c9986eece0811da1423972fdd (patch) | |
| tree | 688b9be43648fbc0f5c07b422b417ef8b69353b3 /llvm/lib/CodeGen/SelectionDAG/InstrEmitter.h | |
| parent | c2493ce4a40be025054087fde59dd0f339baf6c0 (diff) | |
| download | bcm5719-llvm-ba447bae7448435c9986eece0811da1423972fdd.tar.gz bcm5719-llvm-ba447bae7448435c9986eece0811da1423972fdd.zip | |
[AMDGPU] Divergence driven ISel. Assign register class for cross block values according to the divergence.
Details: To make instruction selection really divergence driven it is necessary to assign
the correct register classes to the cross block values beforehand. For the divergent targets
same value type requires different register classes dependent on the value divergence.
Reviewers: rampitec, nhaehnle
Differential Revision: https://reviews.llvm.org/D59990
This commit was reverted because of the build failure.
The reason was mlformed patch.
Build failure fixed.
llvm-svn: 361741
Diffstat (limited to 'llvm/lib/CodeGen/SelectionDAG/InstrEmitter.h')
| -rw-r--r-- | llvm/lib/CodeGen/SelectionDAG/InstrEmitter.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.h b/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.h index 3188c2678f1..42f7846fe7c 100644 --- a/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.h +++ b/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.h @@ -83,7 +83,7 @@ class LLVM_LIBRARY_VISIBILITY InstrEmitter { /// supports SubIdx sub-registers. Emit a copy if that isn't possible. /// Return the virtual register to use. unsigned ConstrainForSubReg(unsigned VReg, unsigned SubIdx, MVT VT, - const DebugLoc &DL); + bool isDivergent, const DebugLoc &DL); /// EmitSubregNode - Generate machine code for subreg nodes. /// |
