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author | Krzysztof Parzyszek <kparzysz@codeaurora.org> | 2018-12-14 20:14:12 +0000 |
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committer | Krzysztof Parzyszek <kparzysz@codeaurora.org> | 2018-12-14 20:14:12 +0000 |
commit | 6b01d35497e21cbb6b61bf123bf0f52c0050515d (patch) | |
tree | 4fd3a448248b618ddcd697d7d2d74bec49844023 /llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp | |
parent | ea9d90083fb096dc210c7a05f60cbce2af83f6ad (diff) | |
download | bcm5719-llvm-6b01d35497e21cbb6b61bf123bf0f52c0050515d.tar.gz bcm5719-llvm-6b01d35497e21cbb6b61bf123bf0f52c0050515d.zip |
[SDAG] Ignore chain operand in REG_SEQUENCE when emitting instructions
llvm-svn: 349186
Diffstat (limited to 'llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp')
-rw-r--r-- | llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp b/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp index b51c23c6a74..da6d973e0b7 100644 --- a/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp @@ -652,6 +652,10 @@ void InstrEmitter::EmitRegSequence(SDNode *Node, const MCInstrDesc &II = TII->get(TargetOpcode::REG_SEQUENCE); MachineInstrBuilder MIB = BuildMI(*MF, Node->getDebugLoc(), II, NewVReg); unsigned NumOps = Node->getNumOperands(); + // REG_SEQUENCE can "inherit" a chain from a subnode. + if (NumOps && Node->getOperand(NumOps-1).getValueType() == MVT::Other) + --NumOps; // Ignore chain if it exists. + assert((NumOps & 1) == 1 && "REG_SEQUENCE must have an odd number of operands!"); for (unsigned i = 1; i != NumOps; ++i) { |