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| author | Simon Pilgrim <llvm-dev@redking.me.uk> | 2017-05-09 13:14:40 +0000 |
|---|---|---|
| committer | Simon Pilgrim <llvm-dev@redking.me.uk> | 2017-05-09 13:14:40 +0000 |
| commit | ca3a63a849ee7253dbbb6d6b2d59513b79ad6405 (patch) | |
| tree | 9a9d169536c5592098c3a1b2fc22e315b1d7d1c3 /llvm/lib/CodeGen/SelectionDAG/FastISel.cpp | |
| parent | e8da53f4e07eea1488eeaf1684f15aac0cf447e7 (diff) | |
| download | bcm5719-llvm-ca3a63a849ee7253dbbb6d6b2d59513b79ad6405.tar.gz bcm5719-llvm-ca3a63a849ee7253dbbb6d6b2d59513b79ad6405.zip | |
[X86][SSE42] Lower v2i64/v4i64 ASHR(X, 63) as PCMPGTQ(0, X)
Similar to what we do for vXi8 ASHR(X, 7), use SSE42's PCMPGTQ to splat the sign instead of using the PSRAD+PSHUFD.
Avoiding bitcasts this improves combines that utilize computeNumSignBits, permits memory folding and reduces pipe pressure. Although it does require a second register, given that this is a (cheap) zero register the impact is minimal.
Differential Revision: https://reviews.llvm.org/D32973
llvm-svn: 302525
Diffstat (limited to 'llvm/lib/CodeGen/SelectionDAG/FastISel.cpp')
0 files changed, 0 insertions, 0 deletions
