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author | Cameron McInally <cameron.mcinally@nyu.edu> | 2018-10-25 18:09:33 +0000 |
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committer | Cameron McInally <cameron.mcinally@nyu.edu> | 2018-10-25 18:09:33 +0000 |
commit | 384a74b0e63d847650e10ac7886fdadd44fc431c (patch) | |
tree | 5b9f21624640b03d7a423ebeacb1b3135c38128b /llvm/lib/CodeGen/SelectionDAG/FastISel.cpp | |
parent | 9db06423d1c2744da799a2e118667bf1723843a6 (diff) | |
download | bcm5719-llvm-384a74b0e63d847650e10ac7886fdadd44fc431c.tar.gz bcm5719-llvm-384a74b0e63d847650e10ac7886fdadd44fc431c.zip |
[FPEnv] Last BinaryOperator::isFNeg(...) to m_FNeg(...) changes
Replacing BinaryOperator::isFNeg(...) to avoid regressions when we
separate FNeg from the FSub IR instruction.
Differential Revision: https://reviews.llvm.org/D53650
llvm-svn: 345295
Diffstat (limited to 'llvm/lib/CodeGen/SelectionDAG/FastISel.cpp')
-rw-r--r-- | llvm/lib/CodeGen/SelectionDAG/FastISel.cpp | 13 |
1 files changed, 8 insertions, 5 deletions
diff --git a/llvm/lib/CodeGen/SelectionDAG/FastISel.cpp b/llvm/lib/CodeGen/SelectionDAG/FastISel.cpp index 542cc10371e..035844294f4 100644 --- a/llvm/lib/CodeGen/SelectionDAG/FastISel.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/FastISel.cpp @@ -89,6 +89,7 @@ #include "llvm/IR/Mangler.h" #include "llvm/IR/Metadata.h" #include "llvm/IR/Operator.h" +#include "llvm/IR/PatternMatch.h" #include "llvm/IR/Type.h" #include "llvm/IR/User.h" #include "llvm/IR/Value.h" @@ -110,6 +111,7 @@ #include <utility> using namespace llvm; +using namespace PatternMatch; #define DEBUG_TYPE "isel" @@ -1692,7 +1694,10 @@ void FastISel::finishCondBranch(const BasicBlock *BranchBB, /// Emit an FNeg operation. bool FastISel::selectFNeg(const User *I) { - unsigned OpReg = getRegForValue(BinaryOperator::getFNegArgument(I)); + Value *X; + if (!match(I, m_FNeg(m_Value(X)))) + return false; + unsigned OpReg = getRegForValue(X); if (!OpReg) return false; bool OpRegIsKill = hasTrivialKill(I); @@ -1782,11 +1787,9 @@ bool FastISel::selectOperator(const User *I, unsigned Opcode) { return selectBinaryOp(I, ISD::FADD); case Instruction::Sub: return selectBinaryOp(I, ISD::SUB); - case Instruction::FSub: + case Instruction::FSub: // FNeg is currently represented in LLVM IR as a special case of FSub. - if (BinaryOperator::isFNeg(I)) - return selectFNeg(I); - return selectBinaryOp(I, ISD::FSUB); + return selectFNeg(I) || selectBinaryOp(I, ISD::FSUB); case Instruction::Mul: return selectBinaryOp(I, ISD::MUL); case Instruction::FMul: |