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| author | Chandler Carruth <chandlerc@gmail.com> | 2014-09-15 20:09:47 +0000 |
|---|---|---|
| committer | Chandler Carruth <chandlerc@gmail.com> | 2014-09-15 20:09:47 +0000 |
| commit | 204ad4c613a1e29de9279fdfb61d69e2b917c00f (patch) | |
| tree | 239ad0c1577c92aa8192feecdbcd7fc7e5bff291 /llvm/lib/CodeGen/SelectionDAG/FastISel.cpp | |
| parent | 7b0917a0c5a7b015e521c2ea719fdddc7f7b0d66 (diff) | |
| download | bcm5719-llvm-204ad4c613a1e29de9279fdfb61d69e2b917c00f.tar.gz bcm5719-llvm-204ad4c613a1e29de9279fdfb61d69e2b917c00f.zip | |
[x86] Start fixing our emission of ADDSUBPS and ADDSUBPD instructions by
introducing a synthetic X86 ISD node representing this generic
operation.
The relevant patterns for mapping these nodes into the concrete
instructions are also added, and a gnarly bit of C++ code in the
target-specific DAG combiner is replaced with simple code emitting this
primitive.
The next step is to generically combine blends of adds and subs into
this node so that we can drop the reliance on an SSE4.1 ISD node
(BLENDI) when matching an SSE3 feature (ADDSUB).
llvm-svn: 217819
Diffstat (limited to 'llvm/lib/CodeGen/SelectionDAG/FastISel.cpp')
0 files changed, 0 insertions, 0 deletions
