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| author | Jakob Stoklund Olesen <stoklund@2pi.dk> | 2012-05-20 06:38:37 +0000 |
|---|---|---|
| committer | Jakob Stoklund Olesen <stoklund@2pi.dk> | 2012-05-20 06:38:37 +0000 |
| commit | 1f1c6add10eaad2908978b7ba6c3485a58f29d72 (patch) | |
| tree | 51ef0cea0ea3a43de185f5d7e29f8edd6e57422e /llvm/lib/CodeGen/SelectionDAG/FastISel.cpp | |
| parent | a103a516c6f516ef2fa104718594515cae5a00b9 (diff) | |
| download | bcm5719-llvm-1f1c6add10eaad2908978b7ba6c3485a58f29d72.tar.gz bcm5719-llvm-1f1c6add10eaad2908978b7ba6c3485a58f29d72.zip | |
Properly constrain register classes for sub-registers.
Not all GR64 registers have sub_8bit sub-registers.
llvm-svn: 157150
Diffstat (limited to 'llvm/lib/CodeGen/SelectionDAG/FastISel.cpp')
| -rw-r--r-- | llvm/lib/CodeGen/SelectionDAG/FastISel.cpp | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/llvm/lib/CodeGen/SelectionDAG/FastISel.cpp b/llvm/lib/CodeGen/SelectionDAG/FastISel.cpp index 0c1ac6982d2..07687ef8b58 100644 --- a/llvm/lib/CodeGen/SelectionDAG/FastISel.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/FastISel.cpp @@ -1345,6 +1345,8 @@ unsigned FastISel::FastEmitInst_extractsubreg(MVT RetVT, unsigned ResultReg = createResultReg(TLI.getRegClassFor(RetVT)); assert(TargetRegisterInfo::isVirtualRegister(Op0) && "Cannot yet extract from physregs"); + const TargetRegisterClass *RC = MRI.getRegClass(Op0); + MRI.constrainRegClass(Op0, TRI.getSubClassWithSubReg(RC, Idx)); BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY), ResultReg) .addReg(Op0, getKillRegState(Op0IsKill), Idx); |
