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authorMatthias Braun <matze@braunis.de>2015-08-26 01:38:00 +0000
committerMatthias Braun <matze@braunis.de>2015-08-26 01:38:00 +0000
commit17af60779654e74ba6e635581d456213b762462f (patch)
tree79895c3ee1101c816aeba149d6af462c81da6bfe /llvm/lib/CodeGen/SelectionDAG/FastISel.cpp
parent1a4aa1589bb4592cca4384851e0ea65727df8e80 (diff)
downloadbcm5719-llvm-17af60779654e74ba6e635581d456213b762462f.tar.gz
bcm5719-llvm-17af60779654e74ba6e635581d456213b762462f.zip
FastISel: Factor out common code; NFC intended
This should be no functional change but for the record: For three cases in X86FastISel this will change the order in which the FalseMBB and TrueMBB of a conditional branch is addedd to the successor/predecessor lists. llvm-svn: 245997
Diffstat (limited to 'llvm/lib/CodeGen/SelectionDAG/FastISel.cpp')
-rw-r--r--llvm/lib/CodeGen/SelectionDAG/FastISel.cpp12
1 files changed, 12 insertions, 0 deletions
diff --git a/llvm/lib/CodeGen/SelectionDAG/FastISel.cpp b/llvm/lib/CodeGen/SelectionDAG/FastISel.cpp
index 8cf859cf517..d5011d2d62d 100644
--- a/llvm/lib/CodeGen/SelectionDAG/FastISel.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/FastISel.cpp
@@ -1408,6 +1408,18 @@ void FastISel::fastEmitBranch(MachineBasicBlock *MSucc, DebugLoc DbgLoc) {
FuncInfo.MBB->addSuccessor(MSucc, BranchWeight);
}
+void FastISel::finishCondBranch(const BasicBlock *BranchBB,
+ MachineBasicBlock *TrueMBB,
+ MachineBasicBlock *FalseMBB) {
+ uint32_t BranchWeight = 0;
+ if (FuncInfo.BPI)
+ BranchWeight = FuncInfo.BPI->getEdgeWeight(BranchBB,
+ TrueMBB->getBasicBlock());
+ FuncInfo.MBB->addSuccessor(TrueMBB, BranchWeight);
+
+ fastEmitBranch(FalseMBB, DbgLoc);
+}
+
/// Emit an FNeg operation.
bool FastISel::selectFNeg(const User *I) {
unsigned OpReg = getRegForValue(BinaryOperator::getFNegArgument(I));
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