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authorCraig Topper <craig.topper@intel.com>2017-06-16 23:19:12 +0000
committerCraig Topper <craig.topper@intel.com>2017-06-16 23:19:12 +0000
commitea5b8bc9efc8ea6c6a68caa53156ee661ce761b8 (patch)
tree4d240d4dac83e8c612ed8ef311f83e2df93adc80 /llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
parentb681907c509be94e4d8228a75c64dc62e30f1342 (diff)
downloadbcm5719-llvm-ea5b8bc9efc8ea6c6a68caa53156ee661ce761b8.tar.gz
bcm5719-llvm-ea5b8bc9efc8ea6c6a68caa53156ee661ce761b8.zip
[SelectionDAG] Use APInt::isNullValue/isOneValue. NFC
llvm-svn: 305605
Diffstat (limited to 'llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp')
-rw-r--r--llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp4
1 files changed, 2 insertions, 2 deletions
diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index 2d4422d94a1..159c680beb8 100644
--- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -2549,14 +2549,14 @@ SDValue DAGCombiner::visitMUL(SDNode *N) {
!DAG.isConstantIntBuildVectorOrConstantInt(N1))
return DAG.getNode(ISD::MUL, SDLoc(N), VT, N1, N0);
// fold (mul x, 0) -> 0
- if (N1IsConst && ConstValue1 == 0)
+ if (N1IsConst && ConstValue1.isNullValue())
return N1;
// We require a splat of the entire scalar bit width for non-contiguous
// bit patterns.
bool IsFullSplat =
ConstValue1.getBitWidth() == VT.getScalarSizeInBits();
// fold (mul x, 1) -> x
- if (N1IsConst && ConstValue1 == 1 && IsFullSplat)
+ if (N1IsConst && ConstValue1.isOneValue() && IsFullSplat)
return N0;
if (SDValue NewSel = foldBinOpIntoSelect(N))
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