diff options
author | Sanjay Patel <spatel@rotateright.com> | 2018-08-08 23:04:43 +0000 |
---|---|---|
committer | Sanjay Patel <spatel@rotateright.com> | 2018-08-08 23:04:43 +0000 |
commit | e47dc1a40522761752a4bdcb5e23f8147c1da0e2 (patch) | |
tree | 24505b08baeef3434429ef42ba04729feabb13f0 /llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp | |
parent | e327266d45b14b693630be50c0bfa1fce18c66f2 (diff) | |
download | bcm5719-llvm-e47dc1a40522761752a4bdcb5e23f8147c1da0e2.tar.gz bcm5719-llvm-e47dc1a40522761752a4bdcb5e23f8147c1da0e2.zip |
[DAGCombiner] loosen constraints for fsub+fadd fold
isNegatibleForFree() should not matter here (as the test diffs show)
because it's always a win to replace an fsub+fadd with fneg. The
problem in D50195 persists because either (1) we are doing these
folds in the wrong order or (2) we're missing another fold for fadd.
llvm-svn: 339299
Diffstat (limited to 'llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp')
-rw-r--r-- | llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp | 21 |
1 files changed, 7 insertions, 14 deletions
diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp index 9690d2c205a..f78688787dd 100644 --- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp @@ -10940,20 +10940,13 @@ SDValue DAGCombiner::visitFSUB(SDNode *N) { return DAG.getNode(ISD::FADD, DL, VT, N0, GetNegatedExpression(N1, DAG, LegalOperations), Flags); - // If 'unsafe math' is enabled, fold lots of things. - if (Options.UnsafeFPMath) { - // (fsub x, (fadd x, y)) -> (fneg y) - // (fsub x, (fadd y, x)) -> (fneg y) - if (N1.getOpcode() == ISD::FADD) { - SDValue N10 = N1->getOperand(0); - SDValue N11 = N1->getOperand(1); - - if (N10 == N0 && isNegatibleForFree(N11, LegalOperations, TLI, &Options)) - return GetNegatedExpression(N11, DAG, LegalOperations); - - if (N11 == N0 && isNegatibleForFree(N10, LegalOperations, TLI, &Options)) - return GetNegatedExpression(N10, DAG, LegalOperations); - } + if (Options.UnsafeFPMath && N1.getOpcode() == ISD::FADD) { + // X - (X + Y) -> -Y + if (N0 == N1->getOperand(0)) + return DAG.getNode(ISD::FNEG, DL, VT, N1->getOperand(1)); + // X - (Y + X) -> -Y + if (N0 == N1->getOperand(1)) + return DAG.getNode(ISD::FNEG, DL, VT, N1->getOperand(0)); } // FSUB -> FMA combines: |