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authorMatt Arsenault <Matthew.Arsenault@amd.com>2016-07-08 07:05:00 +0000
committerMatt Arsenault <Matthew.Arsenault@amd.com>2016-07-08 07:05:00 +0000
commitc3a6fe6ecd63bb73a605203c9cdce9a5de84d304 (patch)
treee39bf22f8d5aa5564111a6790ca42ca8a0070278 /llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
parentc61bcd80af7d8c0f527aa94f5e4eb4ca63d36f0c (diff)
downloadbcm5719-llvm-c3a6fe6ecd63bb73a605203c9cdce9a5de84d304.tar.gz
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Bug 28444: Fix assertion when extract_vector_elt has mismatched type
For some reason extract_vector_elt is sometimes allowed to have a different result type than the vector element type. llvm-svn: 274829
Diffstat (limited to 'llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp')
-rw-r--r--llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp2
1 files changed, 1 insertions, 1 deletions
diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index 54d348e8911..dc2ff6eb918 100644
--- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -12408,7 +12408,7 @@ SDValue DAGCombiner::visitEXTRACT_VECTOR_ELT(SDNode *N) {
// on the constant elements already work.
if (InVec.getOpcode() == ISD::INSERT_VECTOR_ELT &&
EltNo == InVec.getOperand(2))
- return InVec.getOperand(1);
+ return DAG.getAnyExtOrTrunc(InVec.getOperand(1), SDLoc(N), NVT);
// Transform: (EXTRACT_VECTOR_ELT( VECTOR_SHUFFLE )) -> EXTRACT_VECTOR_ELT.
// We only perform this optimization before the op legalization phase because
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