diff options
| author | Chris Lattner <sabre@nondot.org> | 2006-01-12 18:57:33 +0000 |
|---|---|---|
| committer | Chris Lattner <sabre@nondot.org> | 2006-01-12 18:57:33 +0000 |
| commit | b1ee616de99c5964f85bcff863930bf9fd7e42d3 (patch) | |
| tree | ff2f2e1a468c4624de0deba1f306b8d6b9693ef9 /llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp | |
| parent | 556f14a6cb530d6c9a1baf6df8d24da7d440b0fb (diff) | |
| download | bcm5719-llvm-b1ee616de99c5964f85bcff863930bf9fd7e42d3.tar.gz bcm5719-llvm-b1ee616de99c5964f85bcff863930bf9fd7e42d3.zip | |
Don't create rotate instructions in unsupported types, because we don't have
promote/expand code yet. This fixes the 177.mesa failure on PPC.
llvm-svn: 25250
Diffstat (limited to 'llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp')
| -rw-r--r-- | llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp index 1d356689fb8..cb80e250380 100644 --- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp @@ -1184,7 +1184,7 @@ SDOperand DAGCombiner::visitOR(SDNode *N) { // check for rotl, rotr if (N0.getOpcode() == ISD::SHL && N1.getOpcode() == ISD::SRL && N0.getOperand(0) == N1.getOperand(0) && - TLI.isOperationLegal(ISD::ROTL, VT)) { + TLI.isOperationLegal(ISD::ROTL, VT) && TLI.isTypeLegal(VT)) { // fold (or (shl x, C1), (srl x, C2)) -> (rotl x, C1) if (N0.getOperand(1).getOpcode() == ISD::Constant && N1.getOperand(1).getOpcode() == ISD::Constant) { @@ -1206,7 +1206,7 @@ SDOperand DAGCombiner::visitOR(SDNode *N) { if (ConstantSDNode *SUBC = dyn_cast<ConstantSDNode>(N0.getOperand(1).getOperand(0))) if (SUBC->getValue() == OpSizeInBits) { - if (TLI.isOperationLegal(ISD::ROTR, VT)) + if (TLI.isOperationLegal(ISD::ROTR, VT) && TLI.isTypeLegal(VT)) return DAG.getNode(ISD::ROTR, VT, N0.getOperand(0), N1.getOperand(1)); else |
