summaryrefslogtreecommitdiffstats
path: root/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
diff options
context:
space:
mode:
authorRenato Golin <renato.golin@linaro.org>2016-03-02 19:35:45 +0000
committerRenato Golin <renato.golin@linaro.org>2016-03-02 19:35:45 +0000
commit93e42d99347ac36a19ba3e08108ccd1d9c8f1ff4 (patch)
tree95e9ace782deee66655274aff5dd61373db49deb /llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
parentcbbaeb13074400ead830be88143c31e7aac3c01c (diff)
downloadbcm5719-llvm-93e42d99347ac36a19ba3e08108ccd1d9c8f1ff4.tar.gz
bcm5719-llvm-93e42d99347ac36a19ba3e08108ccd1d9c8f1ff4.zip
[ARM] Merging 64-bit divmod lib calls into one
When div+rem calls on the same arguments are found, the ARM back-end merges the two calls into one __aeabi_divmod call for up to 32-bits values. However, for 64-bit values, which also have a lib call (__aeabi_ldivmod), it wasn't merging the calls, and thus calling ldivmod twice and spilling the temporary results, which generated pretty bad code. This patch legalises 64-bit lib calls for divmod, so that now all the spilling and the second call are gone. It also relaxes the DivRem combiner a bit on the legal type check, since it was already checking for isLegalOrCustom on every value, so the extra check for isTypeLegal was redundant. This patch fixes PR17193 (and a long time FIXME in the tests). llvm-svn: 262507
Diffstat (limited to 'llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp')
-rw-r--r--llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp3
1 files changed, 2 insertions, 1 deletions
diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index 216389ac42a..a81cb664584 100644
--- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -2153,8 +2153,9 @@ SDValue DAGCombiner::useDivRem(SDNode *Node) {
if (Node->use_empty())
return SDValue(); // This is a dead node, leave it alone.
+ // DivMod lib calls can still work on non-legal types if using lib-calls.
EVT VT = Node->getValueType(0);
- if (!TLI.isTypeLegal(VT))
+ if (VT.isVector() || !VT.isInteger())
return SDValue();
unsigned Opcode = Node->getOpcode();
OpenPOWER on IntegriCloud