[DAGCombiner] simplify div/rem-by-0

Refactoring of duplicated code and more fixes to follow.

This is motivated by the post-commit comments for r296699:
http://lists.llvm.org/pipermail/llvm-commits/Week-of-Mon-20170306/435182.html

Ie, we can crash if we're missing obvious simplifications like this that
exist in the IR simplifier or if these occur later than expected.

The x86 change for non-splat division shows a potential opportunity to improve
vector codegen: we assumed that since only one lane had meaningful results, we
should do the math in scalar. But that means moving back and forth from vector
registers.

llvm-svn: 297026

1 files changed, 10 insertions, 1 deletions

diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index 4c2135e665d..b228f1e3cbb 100644
--- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -2463,6 +2463,9 @@ SDValue DAGCombiner::visitSDIV(SDNode *N) {
   // X / undef -> undef
   if (N1.isUndef())
     return N1;
+  // X / 0 --> undef (we don't need to preserve faults!)
+  if (N1C && N1C->isNullValue())
+    return DAG.getUNDEF(VT);
 
   return SDValue();
 }
@@ -2538,6 +2541,9 @@ SDValue DAGCombiner::visitUDIV(SDNode *N) {
   // X / undef -> undef
   if (N1.isUndef())
     return N1;
+  // X / 0 --> undef (we don't need to preserve faults!)
+  if (N1C && N1C->isNullValue())
+    return DAG.getUNDEF(VT);
 
   return SDValue();
 }
@@ -2618,7 +2624,10 @@ SDValue DAGCombiner::visitREM(SDNode *N) {
   // X % undef -> undef
   if (N1.isUndef())
     return N1;
-
+  // X % 0 --> undef (we don't need to preserve faults!)
+  if (N1C && N1C->isNullValue())
+    return DAG.getUNDEF(VT);
+  
   return SDValue();
 }